TWEPP 2011 Topical Workshop on Electronics for Particle Physics

Session

B3a - Programmable Logic, design tools and methods

B3a

Sep 28, 2011, 9:50 AM

Vienna, Austria

Conveners

B3a - Programmable Logic, design tools and methods

• Magnus Hansen (CERN)

3. A Low-Power Wave Union TDC Implemented in FPGA

Dr Jinyuan Wu (FERMILAB)

9/28/11, 9:50 AM

Logic

Oral

A low-power time-to-digital convertor (TDC) for an application inside vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to...

79. A 32-Channel High Resolution (<15 ps RMS) Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA)

Mr Cahit Ugur (GSI Helmholtzzentrum für Schwerionenforschung)

9/28/11, 10:15 AM

Logic

Oral

A 32-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine-time calculations are achieved by using the dedicated carry-chain lines. A low latency (30 ns) encoder handles the conversion of the fine time measurement. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and...