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11–13 Jun 2024
CERN
Europe/Zurich timezone
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Porting MADGRAPH to FPGA using High-Level Synthesis (HLS)

12 Jun 2024, 14:05
20m
30/7-018 - Kjell Johnsen Auditorium (CERN)

30/7-018 - Kjell Johnsen Auditorium

CERN

190
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Algorithm implementation in HDL and HLS Algorithm implementation

Speaker

Hector Gutierrez Arance (Univ. of Valencia and CSIC (ES))

Description

The escalating demand for data processing in particle physics research has spurred the exploration of novel technologies to enhance efficiency and speed of calculations. This study presents the development of a port of MADGRAPH, a widely used tool in particle collision simulations, to FPGA using High-Level Synthesis (HLS).
Experimental evaluation is ongoing, but preliminary assessments suggest a promising enhancement in calculation speed compared to traditional CPU implementations. This potential improvement could enable the execution of more complex simulations within shorter timeframes.
This study describes the complex process of adapting MADGRAPH to FPGA using HLS, focusing on optimizing algorithms for parallel processing. These advancements could enable faster execution of complex simulations, highlighting FPGA's crucial role in advancing particle physics research.

Talk's Q&A During the talk
Talk duration 15'+7'
Will you be able to present in person? Yes

Author

Hector Gutierrez Arance (Univ. of Valencia and CSIC (ES))

Presentation materials