1st FPGA Developers' Forum (FDF) meeting

Session

Algorithm implementation

12 Jun 2024, 11:15

30/7-018 - Kjell Johnsen Auditorium (CERN)

Conveners

Algorithm implementation: Late morning

• Davide Cieri (Max Planck Society (DE))
• Rui Zou (Cornell University (US))

Algorithm implementation: Afternoon

• Davide Cieri (Max Planck Society (DE))
• Rui Zou (Cornell University (US))

65. A Neural Network-based trigger for detecting ultra-high-energy neutrinos for RNO-G and IceCube-Gen2

Pawel Marciniewski (Uppsala University), Mr Pawel Marciniewski (Uppsala University)

12/06/2024, 11:15

Algorithm implementation in HDL and HLS

Ultra-high-energy (UHE) neutrinos can be detected via radio antennas installed in polar ice sheets. In this work, we present a trigger system utilizing a convolutional neural network to process the antenna signals. This system can increase the neutrino detection rate by up to a factor of two at negligible additional costs, which would substantially advance UHE neutrino science. The trigger...

20. Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor

Stephan van Beek (MathWorks)

12/06/2024, 11:45

Algorithm implementation in HDL and HLS

Artificial intelligence (AI) is everywhere. Automated image analysis, autonomous driving, industrial inspection, there are many applications today that could benefit from AI. Deep Learning is the most successful solution for image-based object classification, and for most practical applications it requires performant platforms like FPGAs and SoCs.

Designing AI for embedded devices such as...

8. Tree Tensor Network inference on FPGA

Lorenzo Borella (Universita e INFN, Padova (IT))

12/06/2024, 13:45

Algorithm implementation in HDL and HLS

TTNs are hierarchical tensor structures commonly used for representing many-body quantum systems but can also be applied to ML tasks such as classification or optimization. The algorithmic nature of TTNs makes them easily deployable on FPGAs, which are naturally suitable for concurrent tasks like matrix multiplications. Moreover, the hardware resource limitation can be optimally tuned...

43. Porting MADGRAPH to FPGA using High-Level Synthesis (HLS)

Hector Gutierrez Arance (Univ. of Valencia and CSIC (ES))

12/06/2024, 14:05

Algorithm implementation in HDL and HLS

The escalating demand for data processing in particle physics research has spurred the exploration of novel technologies to enhance efficiency and speed of calculations. This study presents the development of a port of MADGRAPH, a widely used tool in particle collision simulations, to FPGA using High-Level Synthesis (HLS).
Experimental evaluation is ongoing, but preliminary assessments...

64. Transferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger

David Reikher (Tel Aviv University (IL))

12/06/2024, 14:25

Algorithm implementation in HDL and HLS

An implementation of an ultra-low latency BDT fully evaluated on an FPGA was introduced for 2024 data taking in the ATLAS experiment with inference latency of 60 ns at 200 MHz and full pipelining. The BDT model is synthesized using Conifer and integrated into existing firmware written in VHDL. I will discuss some technical details on how I transferred HLS-generated code into existing firmware....

52. Hardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm

Mattia Ricchi (University of Pisa & INFN, Bologna (IT)), Camilla Marella (University of Bologna)

12/06/2024, 14:45

Algorithm implementation in HDL and HLS

Magnetic Resonance Fingerprinting (MRF) is a fast quantitative MR Imaging technique able to obtain multi-parametric maps with a single acquisition, but data processing is limited by escalating memory and computation needs. Neural Networks (NNs) accelerate reconstruction, but training still requires significant resources. We propose an FPGA-based NN for real-time brain parameter reconstruction...

36. Resource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems

Timo Muscheid

12/06/2024, 15:05

Algorithm implementation in HDL and HLS

Modern experiments in particle physics and astrophysics rely on quantum detectors for superior energy resolutions. These detectors require specialized readout electronics employing frequency division multiplexing. Operational challenges include managing a high number of tones in the transmission lines, which further complicates the FPGA firmware. For instance, the ECHo experiment plans to...

46. Qibosoq: an open-source framework for quantum circuit RFSoC programming

Rodolfo Carobene

12/06/2024, 15:25

Algorithm implementation in HDL and HLS

The control of superconducting qubits, central to quantum computing,
demands precise manipulation of fast microwave pulses. FPGAs offer ideal
versatility for this task. However, due to FPGA complexity, institutions
often opt for costly, pre-made solutions, limiting customization.
We therefore presented Qibosoq, an open-source software package designed
for radio frequency system on chip...

70. Test Abstract

Dr Rui Zou (Cornell University (US))

Sharable HDL cores

test