Conveners
Solutions to everyday digital design problems: Morning
- Paschalis Vichoudis (CERN)
- Filiberto Bonini (CERN)
Timing closure is possibly the most challenging task in the FPGA algorithms design, with the placer quickly becoming the limiting factor at higher frequencies. AMD encourages to do hierarchical placement and turn to gate-level placement as a last resort. I would like to discuss a methodology to do fine-grained hierarchical placement, based on python generation of constraint files, and that...
Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers.
In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation.
While software code compilation may take...
Phase determinism in timing distribution systems is often a requirement in detectors for High Energy Physics. Because of the new goals of high-luminosity, the rate of particle collisions is increasing. To distinguish almost superposed collisions it is required a very accurate timing signal, in the order of a few picoseconds. Commercial components do not met by default this stringent...
Radio Frequency System-on-Chip (RFSoC) is a new type of device produced by Xilinx AMD which combines SoC (Programmable Logic + Processing System) with wideband and high speed and resolution ADCs and DACs. This makes it a great candidate for data-acquisition systems as well as calibration units for various astroparticle experiments, in particular the ones detecting radio frequency signals. The...
Firmware design is a major challenge in LHC experiment upgrades, often leading to significant project delays. While non configurable systems were immediately operational, recent experiences show firmware and hardware readiness can take years. This underscores the need for innovative methods to speed up firmware design and deployment. This study utilizes advanced firmware design techniques,...
