1st FPGA Developers' Forum (FDF) meeting

Session

HDL development, verification, and simulation tools

12 Jun 2024, 16:15

30/7-018 - Kjell Johnsen Auditorium (CERN)

Conveners

HDL development, verification, and simulation tools: Late afternoon

• Nicolo Vladi Biesuz (Universita e INFN, Ferrara (IT))
• Tom Williams (Rutherford Appleton Laboratory (GB))

HDL development, verification, and simulation tools: Morning

• Francesco Gonnella (University of Birmingham (GB))
• Evangelia Gousiou (CERN)

HDL development, verification, and simulation tools: Late morning

• Evangelia Gousiou (CERN)
• Francesco Gonnella (University of Birmingham (GB))

56. High-Level Synthesis for Machine Learning

Nicolo Ghielmetti (CERN)

12/06/2024, 16:15

HDL development tools

hls4ml (High Level Synthesis for Machine Learning) is a tool for translating Neural Networks to synthesizable gateware for FPGAs. The tool is Python software that presents a user-friendly interface to achieve efficient Machine Learning inference in hardware. hls4ml interfaces to the main ML training libraries, as well as their extensions targeting quantized NNs. At the backend of hls4ml are...

5. Under the Canopy: Exploring Conifer for Low-Latency Decision Forests on FPGAs

Sioni Paris Summers (CERN)

12/06/2024, 16:45

HDL development tools

The conifer library is a tool for translating Decision Forests (ensembles of Decision Trees) for latency-optimised inference on FPGAs. Developments to use conifer for trigger selections at the LHC experiments in 2024 are reaching maturity. The tool supports a variety of frontends for the most popular DF training libraries such as xgboost, scikit-learn, and yggdrasil. Multiple FPGA inference...

26. UVVM – An introduction to the world’s fastest growing FPGA verification methodology

Espen Tallaksen

12/06/2024, 17:15

HDL verification and simulation tools

UVVM is the fastest growing FPGA verification methodology – independent of language. This is due to the improvement UVVM yields in both FPGA quality and development time. This open source Library and Methodology has the most extensive VHDL verification support available and lets you verify complex DUTs in a very efficient manner with great testbench overview. And if you have a really simple...

30. LoCod: an open-source hardware/software co-design tool for SoC/FPGA

Florent Manni (CNES)

12/06/2024, 17:55

HDL development tools

LoCod (French acronym for “codesign software”) is an open-source hardware/software codesign tool, targeting Zynq UltraScale+ and NanoXplore NG-Ultra systems-on-chip and could be extended to any heterogenous target including FPGA and processor.
From a C language source code, developers can choose, with basic code decoration, which functions of the algorithms should be implemented on the FPGA...

17. YML2HDL tool

Thiago Costa De Paiva (University of Massachusetts (US))

13/06/2024, 09:00

HDL development tools

As the technology advances, FPGA devices become more powerful and enable more complex projects. As a result, developers with diverse backgrounds, including different hardware description languages, are required to work together. This is increasingly challenging since the current implementation tools impose constraints on mixed language designs. One key hindrance is that custom type libraries...

40. Automatic code generation for managing the firmware and software for configuration/status registers and memories in the ATLAS Level-1 Central Trigger

Anna Malgorzata Kulinska (CERN)

13/06/2024, 09:20

HDL development tools

Large FPGA firmware designs, such as the ones used in the trigger systems of
HEP experiments, typically contain many hundreds of configuration/status
registers and memories. Managing the required HDL code and software for these
can become challenging. We therefore developed a dedicated tool, called
HardwareCompiler, which parses an XML description of the registers and memories
and...

49. Assertion-Based Formal Debugging During RTL Development

N. Engelhardt (YosysHQ)

13/06/2024, 09:40

HDL verification and simulation tools

Traditionally, assertion-based formal verification is performed after RTL development is complete, by a separate team of verification engineers, to comprehensively prove conformance of a design. While this provides the highest safety guarantees, it is also a lengthy endeavour. But it is not necessary to aim to fully prove everything about a design to take advantage of property checkers'...

7. Open source formal verification with SymbiYosis

Yann Thoma (HEIG-VD)

13/06/2024, 10:15

HDL verification and simulation tools

Verification of digital systems is an art, and often implemented through testbenches and functional verification.

Formal verification is an alternative approach where we describe properties representing the expected behaviour of the system. It allows to prove these properties are fulfilled through assertions. It complements traditional behavioural simulations and allows to detect issues...

61. Becoming vendor agnostic with the help of model-based source code generation

Alexander Wirthmüller (MPSI Technologies GmbH)

13/06/2024, 11:15

HDL development tools

The mid-range FPGA market currently sees the introduction of new FPGA(-SoC) devices with attractive specs. This presentation highlights three key areas to avoid vendor lock-in by leveraging OSS model-based source code generation. The use case is a tabletop 3D laser scanner, implemented on FPGA(-SoC) devices of all major vendors.
Firstly, in FPGA designs requiring (CPU) host-based control,...

29. HDL on git (Hog)

Nordin Aranzabal Barrio

13/06/2024, 11:50

HDL development tools

The coordination of firmware development among numerous developers is a major issue in any collaboration.
This requires standardised tools for ensuring binary file traceability and firmware synthesis with Place and Route repeatability.
To address these problems, we present Hog, a free and open-source tool for maintaining HDL on git.
Hog integrates within HDL IDEs (Intel Quartus, MicroSemi...

2. From SysML To RTL

ADAM TAYLOR (Adiuvo Engineering & Training Ltd)

HDL development tools

FPGA design is complex, there are many design tools which allow implementing our design. What is missing however, is the step before implementation, architecture. There is no standard industry tool for developing this, instead engineers use a variety of tools from Draw IO to Visio and power point. All unsuited to the task, what is needed is the ability to create the architecture and from that...