With over 6 million channels, the High Granularity Calorimeter (HGCAL) for the CMS HL-LHC Upgrade presents a unique data challenge. The ECON ASICs provide critical on-detector data reduction for the 40 MHz trigger path (ECON-T) and 750 kHz data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65nm CMOS, are rad-tolerant (600 Mrad) with low power consumption (<2.5 mW/channel)....
The ATLAS experiment requires a high-precision bunch clock distribution for the High-Luminosity upgrade of the Large Hadron Collider. A new trigger and timing distribution system based on FPGA transceivers and high-speed serial links will replace the existing one. In preparation for this upgrade, we characterized the clock phase uncertainty of AMD UltraScale+ transceivers after reset. We found...
The UK was the first to have a National Quantum Technology Programme with the aim of building practical systems that use quantum superposition, entanglement or squeezing to produce new sensors and clocks with improved accuracy over present commercial systems. Many other countries have followed with their own quantum technology programmes either to build quantum computers or to develop quantum...
For the High-Luminosity Large Hadron Collider era, the trigger and data acquisition system of the Compact Muon Solenoid experiment will be entirely replaced. Novel design choices have been explored, including ATCA platforms with SoC controllers and interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger data analysis will be performed through sophisticated...
The New Small Wheel is a detector designed for the CERN ATLAS experiment, ensuring tracking resolution and efficiency in the LHC high-luminosity era. Comprising Micromegas and small-strip Thin Gap Chamber technologies, it reduces the rate of invalid data acquisition requests in a cavern background-sensitive region. The focus of this contribution is the electronics of its trigger processor,...
Phase-2 CMS will replace the trigger and data acquisition system in preparation for the HL-LHC. This upgrade will allow a maximum accept rate of 750kHz and a latency of 12.5us. To achieve this, new electronics and firmware are being designed. We describe the first version of an algorithm capable of detecting and identifying muon showers, running in the first layer of the trigger system.
It...
The FAST3 (Fast Amplifier for Silicon detector for Timing) is a low noise 16-channel ASIC, belonging to the FAST ASIC family. FAST3 has been implemented in UMC 110 nm CMOS technology, and the design has been optimized for the read-out of 50µm-thick LGAD (Low-Gain Avalanche Diode). The figure of merit of FAST3 is the excellent temporal jitter below 20ps in a wide dynamic range of input charge...
The Overlap Muon Track Finder (OMTF) is one of the subsystems of the CMS L1 Trigger. For the High-Luminosity Large Hadron Collider era (CMS phase-2 upgrade), a new version of the OMTF is currently under development. This upgraded version will be implemented on a custom ATCA board X2O, which houses a Xilinx UltraScale+ FPGA and 25 Gbps optical transceivers. This contribution focuses on the...
The HL-LHC has motivated a generalized upgrade in electronic systems across all experiments. In the new electronics architecture for the CMS Drift Tubes detector, the trigger generation moves from on-detector ASICs to the back-end, to be carried out by top-range FPGAs. The new algorithm aims to deliver full-resolution, offline-grade performance in the reconstruction of muon segments. To...
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to ~ 40-50ps per hit. The ETROC2 is the first full size prototype design fully compatible with the final chip specifications for CMS ETL. The ETROC2 chips have been extensively tested over the past year since May 2023, with laser, hadron beam at CERN and electron beam at DESY, with temperature...
We report on the development, implementation, and performance of a fast neural network used to measure the transverse momentum in the CMS Level-1 Endcap Muon Track Finder. The network aims to improve the triggering efficiency of muons produced in the decays of long-lived particles. We implemented it in firmware for a Xilinx Virtex-7 FPGA and deployed it during the LHC Run 3 data-taking in...
The IGNITE project develops technical solutions for the next generation of trackers at colliders. It plans to implement an integrated module, comprising sensor, electronics, and fast readout, aimed at fast 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In the present paper we present measurement results concerning the performance of the...
Highly granular precision timing detectors are required to achieve scientific breakthroughs across HEP, NP, BES, and FES. To enable the development of these detectors, 3D-intgration between advanced sensor wafers and scaled CMOS technology nodes is required but is currently cost-prohibitive for use in scientific applications. Closing this technology gap is the joint SLAC, FNAL and LLNL effort...
The design, testing, system integration and performance of the ATCA processor (APx) boards firmware and software for the Phase 2 CMS trigger upgrade are presented. The 76 boards plus spares comprise the Calorimeter Trigger and half of the Global Track and Correlator Triggers. The production boards are based on the Xilinx VU13P and have 124 25G optical interfaces. A new optical link protocol...
Following the ALICE ITS3 detector development line of wafer-scale monolithic stitched pixel detector prototypes in the TPSCo. 65nm CMOS imaging technology, the MOSAIX chip is the prototype of the final full-size and full-functionality ITS3 sensor.
MOSAIX has a die size of 26.6x1.96 cm2 with >94% of active area. It has 144 sensor tiles which can be powered individually to compensate for...
Efforts aiming at consolidating the powering for the CMS detector have led to the development of a Low Voltage Power Supply (LVPS). The LVPS converts 380 VDC to 12 VDC, suitable for powering the widely used bPOL12V Point-Of-Load DC-DC converter. To limit cables size, the LVPS must be hosted in the CMS experimental cavern, being exposed to ionizing radiation and stray magnetic field of up to...
The Monolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of $26~\textrm{x}~1.4~\textrm{cm}^2$ size with the primary goal of understanding the stitching technique and yield. It is a proof-of-concept chip for the final sensors of the ALICE ITS3 upgrade. Given the large size, high yield is paramount for the ITS3 sensors and an in-depth yield characterization was performed on MOSS...
In preparation of the operation of the CMS electromagnetic calorimeter (ECAL) barrel at the High Luminosity Large Hadron Collider (HL-LHC) the entire on-detector electronics will be replaced. The new readout electronic comprises 12240 very front end (VFE), 2448 front end (FE) and low voltage regulator (LVR) cards arranged into readout towers (RTs) of five VFE, one FE and one LVR cards. The...
The Beam Gas Ionization (BGI) profile monitor, situated within the PS and SPS accelerators, requires a radiation-tolerant readout system to transfer data from the challenging accelerator surroundings to the back-end for processing. Operating 1m below the beam pipe, the front-end must ensure reliability, given limited hardware access, and preserve signal integrity for the high-speed Timepix3...
The RD50-MPW prototypes are High Voltage CMOS pixel chips in the 150 nm technology from LFoundry S.r.l. aimed at developing monolithic silicon sensors with excellent radiation tolerance, fast timing resolution and high granularity for tracking applications in future challenging experiments in physics. RD50-MPW4, the latest prototype within this programme, implements significant improvements...
The APOLLO ATCA platform is an open-source design that separates into a generic "Service Module" (SM) and customizable "Command Module" (CM), allowing cost-effective use in applications such as readout of the inner tracker and Level-1 track trigger for the CMS Phase-II upgrade at the HL-LHC. The SM incorporates an intelligent IPMC, robust power entry and conditioning systems, a powerful...
Firmware testing on actual hardware is an optimal way to validate large-scale FPGA-based trigger/DAQ systems. For the ATLAS Phase-II level-0 muon trigger system's Sector Logic (SL) firmware, a methodology using prototype ATCA-based SL boards was developed, featuring self-complete DAQ, high-statistics test patterns, and various nature of input test data. The design exploits Zynq SoC on the...
HEP data acquisition systems are often built from high-end FPGAs. As such systems scale in the HL-LHC era, severe underutilization of FPGA transceivers can occur because frontend links prioritize radiation hardness and power consumption over raw data bandwidth. This work evaluates recently introduced low-power, low-cost FPGA devices as an alternative building block for future readout...
Deep Neural Networks are increasingly deployed at safety-critical operations. In order to enable this technology for harsh environments that contain high levels of radiation, fault analysis and mitigation is required. In this study, we present a model-based fault injection campaign to analyze the impact of multiple Single-Event Upsets (SEUs) in Deep Neural Networks (DNNs). Furthermore, we...
The data acquisition system of LHCb Upgrade I is a single stage readout followed by event building, real time reconstruction and selection. The current system already has to process 32 Tbps of data, and this will rise to above 200 Tbps with Upgrade II. The new PCIe Gen 5 readout board called PCIe400 embedding the most powerful altera’s Agilex M-series FPGA and 112 Gbps serial links is the...
PixESL is a virtual prototyping framework tailored for forthcoming particle detectors. It aims to enable high-level abstraction for describing detectors developed in High Energy Physics experiments, simulating the entire chain from particle interaction to data packet readout. This contribution describes three different models developed in the PixESL framework for pixel detector applications: a...
A high-performance event-driven readout electronics system based on Timepix4 has been developed for energy-resolved neutron imaging detectors at China Spallation Neutron Source (CSNS). The system achieves a position resolution better than 55 µm and a timing resolution better than 1 µs. The readout electronics feature a large-capacity cache, high readout bandwidth, and FPGA-based hardware...
This work describes a custom electronics board (“PicoTDC board”) developed at INFN Bologna, whose goal is to provide fast timing measurements to generic detectors able to test different front-end electronics using a common FMC interface. The fast timing measurements are achieved using 2 PicoTDC ASICs from CERN, providing 128 channels with 3.05 ps LSB. Design choices and performance of the card...
RDMA communication can be a good solution for many communication use cases, such as in data acquisition systems and any other system requiring high bandwidth and low latency. Multiple options for an RDMA-based communication system have already been tested, such as profiling based on message size and message count, using multiple simultaneous clients for FPGA-based RDMA senders, or streaming...
For the upcoming high-luminosity LHC, the endcap calorimeters of the CMS experiment will be replaced by the high-granularity calorimeter (HGCAL), a sampling calorimeter using both silicon and scintillator as active materials in different regions depending on the radiation dose. This contribution describes the integration details of the scintillator-based front-end into the DAQ readout chain of...
The HKROC is designed to read out the Photo Multiplier Tubes (PMTs) for next-generation neutrino experiments, which involve multi-ton detector with thousands of PMTs. It measures and digitizes the charge (up to 2500 pC) and Time-of-Arrival (ToA) (25 ps), transmitting this data to the back-end electronics. A second prototype of the HKROC, submitted in CMOS 130 nm node by summer 2022, aimed to...
A comprehensive analysis of bandwidth induced bias on Time Of Arrival (ToA) uncertainty, time resolution, and collected charge, across various silicon technologies - 3D, thin planar, and Low-Gain Avalanche Diodes (LGADs) - is presented. Leveraging extensive test-beam data and transfer function de-convolution, analytical signal descriptions for each technology are inferred. Subsequent MC event...
ALTIROC3 is a 2x2 cm² CMOS 130nm ASIC with 225 channels to read-out the new ATLAS HGTD detector for the High Luminosity-LHC upgrade. It was designed using “Digital-On-Top” flow and triplicated for radiation hardness. Chip level IR-Drop analyses were performed to evaluate accurately the power distribution impact, especially for the Time- to- Digital- Converters implemented in each pixel. These...
The Cleopatra ASIC is a 12-channel prototype ASIC for the readout of hydrogenated amorphous silicon sensors used for real-time dosimetry in radiation diagnostic and radiation therapy.
The architecture is based on a current to frequency conversion based on the recycling integrator principle in order to cover a dynamic range of four orders of magnitude with high linearity.
Three different...
We present the running experience of GE1/1, a new muon tracking and triggering station made of Triple-GEM detectors installed in the most forward region of the CMS muon spectrometer. GE1/1 records data since 2022. Each of the 144 detectors has 24 VFAT3, 3 GBTx, 3 VTRx, 2 VTTx and a Virtex-6 FPGA. All powered by 10 FEAST DCDC converters. We will present the GE1/1 electronics performance over...
Driven by advancements in manufacturing technologies, microelectronics has evolved significantly beyond Moore's Law, now embracing "More than Moore".
This shift emphasizes heterogeneous integration and innovative packaging schemes to overcome challenges like interconnect bottlenecks.
3D integration has emerged as a crucial approach, combining miniaturization benefits with new flexibility in...
A High-Voltage CMOS (HV-CMOS) pixel sensor for particle detection in high energy physics experiments, named UKRI-MPW1, has been developed. It has a high breakdown voltage of ~700 V, while keeping the leakage current below 100 $\mathrm{nA/cm^2}$. This is achieved by improving the sensor cross-section with a customised P-Shield layer and using an advanced chip guard ring scheme. With high...
The harsh environment of the High-Luminosity Phase of LHC will force the CMS experiment to replace the present pixel detector with a new Inner Tracker implementing 65 nm CMOS read-out chips (CROC). The modules, i.e. the Inner Tracker subunits, are powered in series and read-out through a sophisticated opto-electrical chain. Full-scale systems are realized and tested for validation and...
For the high-luminosity upgrade of the ATLAS Inner Tracking detector, a new pixel detector will be installed to increase bandwidth and to cope with higher radiation, among other challenges. In this contribution, the design aspects and qualification of the data transmission from pixel modules to optical readout are presented. A focus is put on the data cable bundles and their performance for...
We report characterization results for our new silicon photonic chip for high-speed data transmission, called COTTONTAIL (Chip for detector instrumentation with wavelength division multiplex). Modulation bandwidths of different conventional and radiation-hardened travelling-wave Mach-Zehnder modulators are sufficient for very high data transmission rates. Wavelength filters for wavelength...
This study details the experimental characterization of silicon photonic ring modulators (RMs) and silicon-germanium (SiGe) electro-absorption modulators (EAMs) exposed to 12 MGy(SiO2) total ionizing dose (TID) within INFN’s project FALAPHEL. We extensively report on the evolution of their key performance metrics as a function of TID. These trends are analyzed in relation to the...
T2K is a long baseline neutrino experiment, entering Phase II with a Near Detector upgrade.
A challenge of T2K Phase II is the development and testing of the Front-end electronics boards
(FEB) for the read-out of the Super-FGD, new active tracking neutrino target. We hereby present
the performance tests confirming that the FEB aligns with design requirements, and the hardware
qualification...
In order to reduce the material budget and maximize the active area of sensors used in future experiments, a 30um thick lightweight flex has been produced. The presented fabrication technology coupled with novel interconnection technologies allows for compact packaging with a direct attachment of the chip connection pads to the flex. Beyond interconnection technologies such as Anisotropic...
The bus tapes required for ATLAS ITk strips are very challenging because of the data rates and lengths of the transmission lines. The impedances need to be very well controlled. The designs must allow for sensor operation at 500V. The required quality of the Ni/Au plating for wire bond pads is difficult to achieve for such large tapes. The tapes must be radiation tolerant and we have seen...
For the HL-LHC, the ATLAS experiment will replace its current Inner Detector with an all-silicon Inner Tracker (ITk), consisting of pixel and strip systems. In the end-cap, silicon sensor modules of the strip system are mounted onto support structures called “petals”. To facilitate the assembly of petals, an automated system has been developed for mounting which streamlines the production...
This work presents Twin_Peaks_CFD1, a custom analog front-end card designed for the read-out of PMTs coupled to lanthanum bromide scintillators. It integrates 16 discrete analog constant fraction discriminators (CFDs) on a compact 12x10 cm board, providing precise timing information for nuclear lifetime measurements.
The design emphasizes cost-effectiveness, utilizing off-the-shelf discrete...
Designed for accelerator beam diagnostics and photon science applications, KALYPSO is a line array camera that stands out for its high-speed performance with the ability to operate at rates upto 12 Mfps in continuous readout mode while maintaining full occupancy. In this contribution, the KALYPSO system with sensor based on TI-LGAD is presented. The latest version of this system is employed...
The ATLAS ITk Pixel system requires large-scale flex circuits for low-voltage power, high-voltage sensor bias, and command/data transmission due to tight space constraints. This reports will focus on the design and production of the services that runs from the modules and the first patch panel of the ITk Pixel Outer Barrel. The results from the quality control tests on the pre-production (10%...
Performance results of the new MetaRock 28 nm low-power Analog Front End (AFE) will be presented. The completed 4D design combines a low-power pulse stretching analog TDC with an improved version of the BigRock preamplifier previously described [1,2]. The target timing resolution of the complete system is better than 100 ps RMS for charge inputs of 0.5 fC @ 0.15 fC threshold, at a total power...
The Belle II experiment searches for physics beyond the standard model. Among the intriguing candidates are decays with an offset vertex. However, the current level-1 trigger dismisses these candidates. To address this problem, a new trigger system is required that can identify such decays when they exhibit two tracks from an offset vertex. The approach uses parallel calculations of Hough...
Ever more precise time information is required to separate independent events at planned and proposed particle physics experiments. Typically, a combination of internal gain, very fast amplifiers and complex sampling circuitry are used to achieve this high time resolution. In this contribution a novel circuit to improve the time resolution of a depleted monolithic active pixel sensor (DMAPS)...
This work describes the design, in a 28 nm CMOS technology, of a front-end channel for the readout of pixel sensors in future particle accelerators. The channel being developed leverages the Time-Over-Threshold technique for the numerical conversion of the detector signal amplitude, and includes a low-noise charge sensitive amplifier featuring a compact gain stage architecture. A prototype...
Quality analogue radiation-hardened design in 28nm CMOS is an iterative process best achieved through IP development. Rutherford Appleton Laboratory (RAL) ASIC Design Group has implemented two test-structure ASICs, PURNIX and YELNIX, to validate the performance of circuits up to 1GRAD TID. PURNIX includes essential building-block radiation-hardened IP, while YELNIX includes a prototype LGAD...
We present the R&D of FPMROC, an ASIC for ToF-PET with a fast MCP-PMT (FPMT). The design architecture includes a preamplifier, a discriminator with programmable threshold, a time- to-digital converter, an event builder with a serializer, a clock unit, and a SPI. We aim for a time resolution below 10 ps, matching the targeted FPMT parameters. We are designing the first prototype using a 55 nm...
The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an on-detector ASIC, Monitoring Of Pixel System (MOPS), and channeled to the Detector Control System (DCS) via a newly developed FPGA-based interface known as MOPS-Hub....
The CMS Collaboration will replace its current endcap calorimeters with a new high granularity calorimeter (HGCAL) for operations at the HL-LHC. The HGCAL back-end DAQ system comprises 96 FPGA-based ATCA boards, each processing data from 108 input optical fibres operating at 10 Gb/s. This paper describes in detail the architecture and prototyping of the elementary readout unit in the back-end...
At PSI the future standard hardware platform based on CompactPCI-Serial is already widely spread for developments in several applications and is under discussion for use on all our accelerators.
With the focus on cost optimization smaller sub-racks are now part of the toolbox as well as rear boards with a subtle set of interfaces.
Based on the requirements of a Fill-Pattern Monitor for SLS...
CosmoLink is a compact coincidence detector comprising two scintillators for portable on-site muon flux measurement. The Scintillators are coupled with wavelength shifting (WLS) fibers for efficient light guiding to Silicon photomultipliers (SiPMs). Each readout channels equipped with a Transimpedance preamp, Discriminator and peak hold circuit. Upon successful coincidence trigger the peak...
In High Energy Physics, ASICs are becoming more and more complex with the integration of many digital processing and monitoring structures. The next generation of System-On-Chips will require reprogrammable logic to let the user change the ASIC behavior after its fabrication. CPROC (Central Processing ReadOut Chip) is a processor demonstrator based on the RISC-V Instruction Set Architecture....
This work evaluates the analog performance of n and pMOSFETs in a 28-nm commercially available bulk process in two extreme environments: cryogenic temperatures and ionizing radiation. To this end, a dense array with >2000 devices of various geometries is characterized. Cryogenic characterization is performed down to sub-Kelvin temperatures where CMOS circuits can be used for quantum computing...
Before starting the High-Luminosity Large Hadron Collider (HL-LHC) runs, the CMS detector will be substantially upgraded to cope with the significant increase in instantaneous luminosity. The entire CMS Inner Tracker (IT) detector will be replaced, and the new detector will feature increased radiation hardness, higher granularity, and the capability to handle higher data rates and longer...
The Taishan Antineutrino Observatory (TAO) aims to measure the energy spectrum of reactor antineutrinos, providing a reference spectrum for the JUNO and offering benchmark references for the nuclear databases.
The JUNO-TAO experiment uses 4024 SiPM tiles with 8048 ADC channels to ensure the proposed energy resolution(<1.5% @ 1 MeV), spatial resolution(around 1 cm), and timing...
JUNGFRAU is a state-of-the-art charge-integrating detector for imaging experiments at synchrotrons and free-electron lasers. It is currently limited to a frame rate of 2.2 kHz. With the goal to increase the frame rate of the detector to > 10 kHz, we have designed a 3.125 Gbps high-speed serial readout recently. Thus, the development of a fast Analog-To-Digital Converter ADC has become our...
The CMS Electromagnetic Calorimeter (ECAL) uses lead tungstate scintillating crystals to measure the energy of electrons and photons produced at the Large Hadron Collider (LHC). The High Luminosity upgrade of the LHC (HL-LHC) at CERN during the LHC Long Shutdown 3 imposes significant challenges for its experiments. The higher luminosity changes the environmental conditions in which the ECAL...
The design and simulation results of an ultra-low power fast 10-bit SAR ADC in CMOS 130~nm technology, are presented. This ADC is an extension of experimentally verified (INL,DNL $<$ 0.5~LSB, ENOB$>$9.5) 10-bit SAR ADC working up to 50~MSps and consuming 680~uW@40~MSps. The goal of the new design was to add an internal threshold for the processed input signal, so as to stop the conversion and...
This contribution introduces a novel test system developed to evaluate the signal transmission quality in high-speed data links for the 2026 Inner Tracker upgrade of the ATLAS experiment. Using an FPGA-based data acquisition framework, the setup can run simultaneous Bit Error Rate (BER) tests for many channels and generate virtual eye diagrams, for qualifying the ~26K electrical links of ATLAS...
The CoRDIA X-ray detector is a development targeting experiments at modern diffraction-limited synchrotron rings and free-electron lasers operating either in continuous wave or quasi-continuous long burst modes with photon bunch frequencies up to a few 100kHz. It’s a hybrid detector with sensitive tiles formed by a read-out ASIC bump bonded to a sensor. Since 2020 4 prototype ASICs were...
We developed signal readout electronics for a liquid argon time projection chamber detector, envisioned for use in neutrino oscillation and nucleon decay search experiments. The front-end electronics are based on the ASIC technology, which consists of a 16 channels analog processor, an analog-to-digital converter, and a signal transmitter for digital processing. We demonstrated that the...
The High-Luminosity LHC will start operations for physics in 2029.
The expansion of the dataset will be achieved by increasing the number of collisions per bunch crossing, leading to higher radiation doses and busier events. To cope with those harsher conditions, the ATLAS Liquid Argon Calorimeter readout will be upgraded to be able to efficiently measure the deposited energies.
A new...
The High-Luminosity LHC will start operations for physics in 2029.
This expansion of the dataset will be achieved by increasing the number of collisions per bunch crossing, leading to higher radiation doses and busier events. To cope with those harsher conditions and to be compatible with the new ATLAS data acquisition paradigm, the ATLAS Liquid Argon Calorimeter on-detector electronics...
Validation of the recent FPGA firmware logic used in particle physics is being hard, since the implemented logic becomes larger and more complex with increasing FPGA resources. In order to address efficiently, we have developed a firmware validation system using the FPGA accelerator produced by FPGA vendors. We have established a system by developing the interface with CPU of host computer,...
The design and measurement results of a prototype TDC fabricated in CMOS 130nm technology are presented. The TDC architecture with analog interpolators was chosen, which was motivated by previous experience in ADC design. The measured time difference between the event and the trigger signal is converted to the amplitude and then digitised by a 10-bit ADC. The TDC prototype is functional nad...
The ASIC EICROC is designed to read out the AC-LGAD detectors for the future EIC at Brookhaven National Laboratory (BNL). These detectors should combine excellent temporal (20 ps) and spatial (20 um) resolution, enabling a new generation of pixel detectors with precise time measurement. Designing an ASIC to read out the AC-LGAD detector represents a significant technological challenge. EICROC...
The Embedded Monitoring Processor (EMP) is a state-of-the-art multi-processing System on Chip (MPSoC) based platform, designed for the Detector Control System (DCS) of the ATLAS experiment upgrade. Utilizing the advanced capabilities of the Xilinx Ultrascale+ architecture, the EMP interfaces with the monitoring and control functionalities of its radiation hard front-ends through high-speed...
We present the first version of an enhanced trigger algorithm for drift time detectors an its application in the ATLAS Monitored Drift Tube (MDT) Trigger Processor, key component in the upgrade of the first-level muon trigger for ATLAS at the High-Luminosity LHC.
Motivated by the necessity to minimize the impact of performance degradation of the ATLAS Resistive Plate Chambers due to aging...
At LHC phase 2, the CMS detector electronics need a precise clock to discriminate piled-up events. The backend electronics of the barrel electromagnetic calorimeter (ECAL) supplies the high-precision clock to the frontend. However, after a reset in the deserializer, the resulting phase of the recovered clock is not accurately repetitive. Therefore we have studied a case where the system...
In preparation for the operation at HL-LHC the electronics of the Electromagnetic calorimeter Barrel must be replaced. 12240 new very front end (VFE) cards will amplify and digitize signals of 62100 lead-tungstate crystals instrumented with avalanche photodiodes. 2448 low voltage regulator cards provide power for the VFE and digital interface cards. Reliable operation of these cards with...
During the upcoming Long Shutdown (LS3) of the LHC, the three innermost layers of the ALICE Inner Tracking System (ITS2) will be replaced by ITS3, a new vertex detector utilizing curved, stitched wafer-scale monolithic silicon sensors, fabricated using 65 nm CMOS technology and thinned to 50 μm. The feasibility of this technology for ITS3 was examined in the initial test production run (MLR1)....
The STS detector in the CBM experiment delivers data via multiple E-Links connected to GBTX ASICs. In the process of data aggregation, that data must be received, combined into a smaller number of streams, and packed into so-called microslices containing data from specific periods. The aggregation must consider data randomization due to amplitude-dependent processing time in the FEE ASICs and...
The ATLAS Strip Tracker for HL-LHC consists of individual modules of silicon sensors and front-end electronics. The modules are mounted on carbon-fiber substructures with 14 modules per side. An End-of-Substructure (EoS) card connects up to 28 data lines to lpGBT and VL+ ASICs that provide data serialization and 10 GBit/s optical data transmission to off-detector systems, respectively. The EoS...
For nearly 20 years, the Power Supply and Crate Service at CERN has been responsible for the maintenance tracking of power supplies and crates used by the CERN experiments. With this experience, and with the imminent introduction of a new generation of power supplies for the HL-LHC, the timing is opportune to conduct a statistical analysis to draw lessons from the past and make recommendations...
The CBM experiment uses a free streaming DAQ with interaction rates up to 10MHz resulting in data rates, which exceed storage capabilities, necessitating online processing. The SPADIC ASIC of the CBM-TRD provides hit messages with oscilloscope-like sampling of the detector data, encoding valuable information. To speed up data unpacking and free up computing time, feature extraction is moved to...
The FELIX system, initially deployed for ATLAS in LHC Run 3, will evolve for Run 4, serving all subdetectors. The system will consist of 350 servers with new custom PCIe FELIX cards and 200 GbE interfaces, handling data at 1 MHz readout rate for a 4.6 TB/s throughput. The new PCIe cards, featuring an AMD Versal Premium FPGA/SoC and advanced connectivity, run upgraded firmware to decode data...
New-generation physics detectors create a need for high-speed, high-flexibility datalinks in the community. Specific interest lies with commercial standards, compatible with off-the-shelf hardware, therefore replacing custom backends.
We present encouraging first results of an effort evaluating 100Gb/s Ethernet for data readout in the context of typical High-Energy Physics detector...
The design and measurement results of a SoC readout ASIC, called FLAXE, developed for the ECAL-p, the electromagnetic calorimeter at the LUXE experiment are presented. The FLAXE consists of 32 channels with programmable gain front-end, fully differential shaper, and a 10-bit SAR ADC in each channel, working nominally at 20 MSps. Due to a very low bunch crossing rate of 10Hz foreseen for the...
The use of ultra-lightweight flexible Printed Circuit Boards (PCBs) in silicon-based particle detectors was pioneered for the ALICE Inner Tracking System 1 (ITS1) and the STAR tracker in the early 2000s. These PCBs feature thin, flexible interconnections made of µm-scale polyimide (e.g. kapton) and metal (e.g. copper or aluminum), offering low-mass yet with stability of mechanical and...
MightyPix is the first iteration of a High-Voltage CMOS (HV-CMOS) sensor chip developed for the LHCb Mighty Tracker. The digital readout of this chip is compatible to LHCb specifications. To verify the digital functionality of the chip in an LHCb environment, an emulator has been developed . This setup comprises the FPGA, CERN's developed VLDB, some custom interface boards and support...
Next generation particle physics experiments like Electron Ion Collider (EIC) demand high-speed data communication and lower mass designs for its detectors.
This poster presents initial test results for circuits designed to meet the EIC high-speed data requirements. These include a dual-frequency Phase Locked Loop (PLL) that supports two frequency modes of operation, a 5 GHz Pseudo-Random...
The contribution will concern the analysis of data provided by Gas Electron Multiplier (GEM) detectors already installed in the Compact Muon Solenoid (CMS) experiment. We will focus on the correlations among the baseline current observed in the High Voltage (HV) system, the background radiation, and the Large Hadron Collider (LHC) beam luminosity. Additionally, an update on the discharge rates...
Abstract: We present the architectural design, prototype fabrication and first measurements for the second revision of the High Pitch digitizer System-on-Chip (HPSoC) prototype. The HPSoC concept is that of a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip was fabricated in 65nm...
ITk strip module is the basic unit in ITk strip upgrade. To do an irradiation test for module with smaller size, the collaboration developed a board called BETSEE. We finish BETSEE test with all latest version of ASICs using proton beam at China Spallation Neutron Source, which is the first time using 10(Mrad/h) level dose rate. From our result, SEE effect is acceptable but TID effect become...
The ATLAS collaboration will replace its inner detector by an all-silicon tracker for the HL-LHC.
The new pixel detector will cover a sensitive area of 13m2 with about 9000 modules, made of planar and 3D silicon sensors bump bonded to new Front-End ASIC.
The modules are loaded on carbon structures in the form of (half)rings and staves.
Electrically functional prototypes of these local...
With the streaming data acquisition scheme planned for the CBM experiment, the quality of event reconstruction depends on the accuracy of clock and time distribution. The Timing and Fast Control (TFC) system ensures that all the readout FPGA boards are aligned in time on the sub-clock and the absolute scales. This is achieved by distributing the time information over an optical link with...
The High-Luminosity upgrade of the LHC (HL-LHC) will triple the proton-proton collision rate, posing challenging requirements for the ATLAS trigger and readout system. A low-latency, FPGA-based hardware trigger for muons in the barrel region will be implemented to identify candidates within 1.7 μs from collisions for further refinement by the Monitored-Drift-Tubes-Trigger-Processor. An...
The Phase-II Upgrade of the LHC will increase its instantaneous luminosity by a factor of 7. At the HL-LHC, the number of proton-proton collisions in one bunch crossing increases significantly, putting more stringent requirements on the LHC detectors electronics.
The ATLAS Liquid Argon calorimeter measures the energy of produced particles produced and feeds the ATLAS trigger to identify...
The High Luminosity Large Hadron Collider (HL-LHC) necessitates a complete replacement of the current Compact Muon Solenoid (CMS) silicon tracker due to harsh conditions. The Phase-2 Outer Tracker (OT) is designed with high radiation tolerance, increased granularity, and enhanced data rate handling. It will provide tracking data to the Level-1 trigger, maintaining sustainable trigger rates...
A new on-detector power distribution scheme for the High Granularity Calorimeter (HGCAL) Phase-2 upgrade of CMS is under development. This scheme is based on a heavy-copper flexible printed circuit board (FPC), allowing for an efficient use of the tight integration space, with minimal insulation overhead, excellent electrical and thermal performance and simplified integration, when compared...
The performance of ASICs for high-bandwidth communications is heavily influenced by the interconnection with the hosting module and paired devices, including the bonding scheme and the PCB layout. The validation campaign of the DART28 high-speed transmitter has highlighted that a coordinated simulation and design of the power delivery network is required to obtain satisfactory performance. In...
Silicon particle detectors struggle to follow the miniaturisation of available commercial processes, partially due to the relatively large transistors required for the optimal performance of the analogue frontend. Particam instead uses a digital only approach which is focused on digital storage cells switching due to transient radiation. With a pixel being little more than a memory cell it can...
The data acquisition system of the Micro-Vertex Detector in the PANDA experiment, including the recent advancements in the design of the data concentrator (MDC) ASIC, will be presented. The MDC is a local digital controller on the detector module. The contribution describes the entire readout chain, encompassing the double-side microstrip sensors, the ToASt front-end ASICs, the MDC, the lpGBT...
High-precision time measurements are the latest trend for experiments and PET applications.
Compactness, scalability and applicability to thousands of channels is required for the readout electronics.
CAEN A5203 board, part of a synchronizable and distributable Front-End Readout System (FERS), integrates the CERN picoTDC ASIC on a small unit for high-resolution time measurements of ToA and...
The high luminosity operation of the LHC will deliver collisions with a luminosity about 10 times the original design value. This poses a big challenge for trigger and data acquisition due to nearly 200 overlapping collisions, called pile up, within the same bunch crossing. Disentanglement of the pileup particles from those of interesting physics processes is achieved by implementing the...
Developing a cost-effective single-die pixel-detector hybridization method using Anisotropic Conductive Films (ACF) or Anisotropic Conductive Paste (ACP) aims to replace fine-pitch bump bonding with conductive micro-particle embedding in adhesive film or paste. This technology enables integration of hybrid or monolithic detectors in modules, replacing wire bonding or solder-bumping. Within the...
The COLUTA ASIC is an 8-channel, 15-bit, 40 MSPS, analog-to-digital (ADC) converter designed for the high-luminosity LHC (HL-LHC) upgrade of the Liquid Argon calorimeter readout electronics. The production version of the ADC meets and exceeds the specifications for the analog performance and the HL-LHC radiation tolerance. The production testing will be performed by a custom-designed robotic...
NνDEx-100 is the phase I of NνDEx, which is a proposed 0νββ detection experiment based on the high pressure gaseous TPC filled with SeF6. Thousands of sensors will be placed on the readout plane located in one end-cap of the TPC. The sensors collect ions, measure the charge and output analog waveforms with the integrated CSA. The outputs are then digitized, aggregated, and transmitted to the...
We developed a prototype of muon beam monitor for the COMET experiment. The detector consists of SiC PN-diodes and dedicated readout electronics. By tailing the 256 sensors in a matrix, the beam parameters extracted from this monitor are utilized for the essential background estimation. The electronics is designed in 65 nm CMOS, including 16 channels analog processor, ADC, PLL, and CML...
Next-generation silicon pixel detectors with fine granularity will allow for precise measurements of particle tracks in both space and time. A reduction in the size of pixel data must be applied at the collision rate of 40MHz to fully exploit the pixel detector information of every interaction for physics analysis.
We developed radiation hard readout integrated circuit with on-chip digital...
Results are presented for reliability tests of the SFP+ transceivers and the readout board of Thin Gap Chambers (TGC) for the ATLAS experiment at HL-LHC. The radiation tolerance was evaluated for the SFP+ transceivers from Broadcom and FS and the TGC frontend board with gamma ray irradiation up to O(100) Gy at the Cobalt-60 facility of Nagoya University. An accelerated aging test was also...
Based on the fourth generation synchrotron radiation light source, the stability of X-ray beam is an urgent problem to be solved in current cutting-edge experiments. This project is based on fast response time of diamond detectors. A fast response four channel weak current measurement and data acquisition circuit based on diamond detectors was developed using ADA4530. Experimental tests show...
Special considerations have been made in the design to reduce digital state changes and ensure reliable operation, we tested the effectiveness of the protection by running separate chips inside the proton beam, and layout is that all chips concurrently fit into a 20 mm beam spot. The
study of corrected bit flips in registers and actual SEEs in LCB and LP path is carried out under different...
Monolithic active pixel sensors are considered as the nominal choice for a large variety of particle physics experiments. Consequently, the design of pixel matrices faces a wide range of specifications.
We developed a pixel matrix read-out architecture based on the local interconnection of asynchronous N:1 time arbiters with fixed priority. This architecture is not limited by global signals...
The ALICE experiment at the Large Hadron Collider (LHC) has planned an upgrade of the Inner Tracking System, ITS3, which will be installed during the LHC Long Shutdown 3 (LS3, 2026-2028). This presentation will show fresh results about the resolution performance obtained at the end of 2024 with 65 nm CMOS MAPS Analogue Pixel Test Structures during beam tests at CERN SPS. Resolution performance...
In preparation for the High-Luminosity-Upgrade of the Large Hadron Collider, new silicon strip detector modules need to be built for the ATLAS ITk strip tracker. The powerboard flexes in ITk strip modules are responsible for powering all readout electronics as well as controlling and monitoring module voltages, currents and temperatures. In total, about 6000 end-cap powerboards need to be...
To cope with the increase of the LHC instantaneous luminosity, new trigger readout electronics were installed on the ATLAS Liquid Argon Calorimeters.
On the detector, new electronic boards digitise 10 times more signals than the legacy system. Downstream, large FPGAs are processing up to 20 Tbps of data to compute the deposited energies. Moreover, a new control and monitoring infrastructure...
The Global Trigger will be the final stage of the new Level-1 trigger for Phase-2 operation of CMS. Based on high-precision inputs from the muon-, calorimeter-, track- and particle flow triggers, it will evaluate a menu of O(1000) cut-based and machine-learning-based algorithms in a system of up to thirteen Serenity processing boards equipped with AMD Ultrascale+ FPGAs and interconnected with...
To mitigate the impacts of pileup caused by luminosity increase in the ATLAS Phase-II upgrade, the High Granularity Timing Detector (HGTD) is proposed to measure the timing of tracks precisely. The Peripheral Electronics Board (PEB) is an important part of the HGTD, which acts as a bridge between the front-end modules and the off-detector electronics. We have designed and produced a prototype...
High-voltage CMOS Pixel technology is being considered for future Higgs factory experiments. The ATLASPix3.1 chip, with a pitch of 50μm x 150μm, fabricated using TSI 180nm HV-CMOS technology, is a full reticle-size monolithic HV-CMOS sensor with shunt-low dropout regulators that allow serial powering for multiple sensors. A beam test was conducted at DESY using 3-6 GeV positron beams, with...
A very low power frontend circuit using the compensating common-gate scheme is described. It combines features of the regular common-gate topology and the trans-impedance amplifier (TIA) schemes allowing designers to achieve low input impedance and sufficient bandwidth with small power consumption. It can be used as an interface between detectors and the pseudo-thyristors we developed to...
The ATLAS experiment is preparing for the High-Luminosity LHC era, by replacing the current innermost detector with an advanced all-silicon tracker (pixels and strips) to withstand radiation damage and increased particle activity. Pixel module quality control spans various production stages which necessitates a robust data acquisition software capable of handling high data rates and MHz...
The COMET (COherent Muon to Electron Transition) experiment at J-PARC requires particle detectors on the beam axis for proton and muon-pion flux monitoring. The GAROP-2 (GAted-ReadOut Proton 2) is thus dedicatedly developed as the read-out electronics for the diamond or SiC monitors. The detectors and GAROP-2 are gated off at the proton pulse phase to prevent it from saturation. Added to this...
After Run III the ATLAS detector will undergo many upgrades to cope with the harsher radiation environment and increased number of proton interactions in the high luminosity phase of the LHC. One key project of this upgrade is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out at 1,28Gb/s with a BER at 95%CL less than 10^-12. The Optosystem performs opto-electrical...
The HGTD is a novel detector introduced to augment the new all-silicon Inner Tracker in the pseudo-rapidity range from 2.4 to 4.0, adding the capability to measure charged-particle trajectories in time as well as space. A prototype of Peripheral Electronics Board (PEB), which supports up to 55 front-end modules with 12 lpGBT, 9 VTRx+ and 52 bPOL12v, is developed to work as a bridge between the...
Resistive Plate Chambers (RPCs) are versatile detectors widely used in HEP experiments due to their excellent timing resolution and efficiency. However, conventional gas mixtures used in RPCs include C2H2F4 and SF6, freon-based gas mixtures with high global warming potential (GWP). So, a transition to eco-friendly gas is necessary to reduce the environmental impact and long-term operation of...
In this talk, we report the R\&D program underway at CCNU to develop a pixel chip for the readout of GEM detectors appropriate for use in the CSR external-target experiment (CEE) at HIRFL for beam monitoring. The chip offers simultaneous time-over-threshold (TOT) and time-of-arrival (TOA) measurements, and a data-driven readout scheme with a rate of 40 MPixels/s. Two generations of the chips...
This work focuses on Total Ionizing Dose (TID) test of LVDS receivers that will be used for the readout system of the ATLAS muon barrel spectrometer within the High Luminosity (HL)-LHC program. We designed an experimental setup that allows to investigate TID effects on power consumption and signal integrity, including variations in amplitude, rise/fall time, jitter, signal-to-noise ratio, as...
The Compressed Baryonic Matter experiment (CBM) at FAIR shall address studying the hadronic phase diagram at high densities and moderate temperatures. Several particle detectors compose the CBM, including a Ring Imaging Cherenkov (RICH) counter. We present the design implementation of an 8×8 SiPM array adapted to the readout electronics of the CBM’s RICH. We also analyze the performance of a...
This contribution presents the methodology and verification strategy for OBELIX, the monolithic active pixel CMOS sensor designed for the proposed upgrade of the Belle II vertex detector. Leveraging a dual verification approach with cocotb and UVM, we ensure the integrity of OBELIX's digital logic. This methodology addresses the complexities of ASIC design, which includes an 896x464 pixel...
