1–13 Sept 2025
University of Pisa and INFN Sezione di Pisa
Europe/Zurich timezone

DISAGGREGATING SYSTEM ARCHITECTURES (e.g. MEMORY SYSTEMS) FOR FUTURE HPC AND ARTIFICIAL INTELLIGENCE WORKLOAD

9 Sept 2025, 09:40
50m
University of Pisa and INFN Sezione di Pisa

University of Pisa and INFN Sezione di Pisa

Speaker

Robert PATTI (CeO NHanced-Semiconductors, USA)

Description

With staff experience averaging more than 20 years, our seasoned team of design engineers and manufacturing professionals have solid expertise in high-density, low-power products. They work in deep submicron nodes with a keen eye for cost-size-weight reduction and design sustainability. They have created sensors, FPGAs, SerDes, memory chips (DRAM, MRAM, and RRAM), ASICs, AI systems, and many other ingenious devices.

As pioneers in advanced packaging and heterogeneous integration, our team boasts an admirable record of creating successful state-of-the-art products.

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