Speaker
Description
We will present a detailed performance assessment of the implemented logic and provide an in-depth discussion of the validation strategy and methodology, which has been successfully integrated into our development workflow for the muon reconstruction in the Level-0 (L0) trigger in HL-LHC. The muon trigger will be fully upgraded with a real-time reconstruction system for HL-LHC. The new logic, implemented on a large-scale FPGA, identifies and reconstructs muon tracks using hit coincidences within the same bunch crossing and pattern-finding algorithms realized with Look-Up Tables in RAM. Designed as a pipeline trigger logic, it processes all events from the 40 MHz collision rate with a fixed latency.
To ensure reliability, we have developed a comprehensive verification framework consisting of a test vector generator, bitwise simulator, firmware RTL (register transfer level) simulator, and actual hardware. The firmware has undergone extensive validation using test vectors derived from Monte Carlo simulations. Intensive debugging has resulted in significant improvements, represented by enhanced plateau efficiency and momentum resolution in RTL simulation. The final trigger performance has been evaluated in terms of efficiency as functions of transverse momentum, pseudorapidity, and azimuth angles using a high-statistics dataset of simulated tracks. The performance is well aligned with the expected performance and shows precisely consistent results between bitwise and RTL simulators.
Details
N/A
| Internet talk | No |
|---|---|
| Is this an abstract from experimental collaboration? | Yes |
| Name of experiment and experimental site | ATLAS, CERN |
| Is the speaker for that presentation defined? | No |
