20–23 May 2025
CERN
Europe/Zurich timezone
There is a live webcast for this event.
We published the final schedule of the forum! Discord for QA: https://discord.gg/JMNNjW9T

Open Logic – open-source FPGA Standard Library

20 May 2025, 15:55
35m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
Show room on map
Sharable HDL cores Sharable HDL cores

Speaker

Oliver Bründler (OpenLogic)

Description

Open Logic is the fastest-growing open-source HDL standard library on the market, as measured by GitHub stars. It simplifies FPGA development with reusable, modular, and vendor-independent components. Bridging the gap between hand-optimized HDL code and high-level abstractions like HLS and IP integration, it offers a balanced approach to effort and resource optimization. With a strong focus on code quality, verification, documentation, and ease of use, Open Logic ensures both reliability and accessibility.

This presentation will highlight the library's philosophy, its place in the FPGA design landscape, and the advantages it offers, including device independence and reduced maintenance effort. Attendees will explore key features such as FIFOs, AXI utilities, and CAMs, and discover how to integrate Open Logic effectively into their projects.

Talk's Q&A End of talk
Talk duration 20'+10'
Will you be able to present in person? Yes

Author

Oliver Bründler (OpenLogic)

Presentation materials