Speaker
Description
The high-luminosity environment at Belle II leads to growing beam-induced background, posing major challenges for the Belle II Level-1 (L1) trigger system. To maintain trigger rates within hardware constraints, effective background suppression is essential. Hit filtering algorithms based on Graph Neural Networks (GNNs), including the Interaction Network (IN), have demonstrated successful applications in offline filtering scenarios.
To facilitate GNN-based hit filtering at the L1 trigger level, we adapt existing offline algorithms using state-of-the-art model compression and hardware-aware design techniques. This work presents an end-to-end hardware acceleration pipeline for the IN, considering not only the network itself but also preprocessing steps such as graph building. We optimize for O(1us) latency and high throughput of 32 million events per second while minimising resource utilisation of our neural network through operator fusion, combining graph building with static GNN message-passing operators. To meet Belle II’s real-time demands, we exploit spatial parallelism by partitioning the detector’s 14336 wires into independent FPGA-processing regions.
We validate our approach with a working prototype implemented on the AMD XCVU160 FPGA used in the Belle II Universal Trigger Board 4 (UT4).
Significance
We present a real-time GNN-based hit filtering system deployment on FPGA, processing O(1K) raw detector channels with O(1us) latency and O(10M) events per second on a single FPGA. It enables significant suppression of beam background at an early stage in the trigger chain, ensuring that the Level-1 trigger rate remains within hardware limits under forthcoming high-luminosity conditions and provides a scalable solution for future high-rate collider environments.
| Experiment context, if any | Belle II |
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