Speaker
Description
With plans for upgrading the detector in order to collect data at a luminosity up to 1.5×1034 cm-2s-2 being ironed out (Upgrade II - LHC Run5), the LHCb Collaboration has sought to implement new data taking solutions already starting from the upcoming LHC Run4 (2030-2033).
The first stage of the LHCb High Level Trigger (HLT1), currently implemented on GPUs and aiming at reducing the event rate from 30MHz to 1MHz, relies on track reconstruction at the input rate. With the target of ensuring the continued ability of reconstructing tracks in real-time for all collision events at increased luminosity, a tracking system based on a cluster of interconnected FPGAs has been approved to be built for the upcoming Run4 as an R&D effort: the DoWnstream Tracker (DWT) [1, 2, 3].
By reconstructing track stubs in the SciFi subdetector, downstream to the magnet, the DWT will both provide immediate benefits, by speeding up HLT1 reconstruction, and also give the opportunity for building knowledge and experience on such a system, as an R&D effort itself, in view of the Upgrade II.
The DWT relies on the Artificial Retina architecture, which can be seen as a multidimensional Hough Transform, computed numerically starting from a set of reference tracks, instead of seeking the analytical solutions. Because of this, the computation time of this tracking architecture scales linearly with the number of hits in the detector, instead of their possible combination [4].
Hits are delivered only to the elemental processing units inside the FPGAs which reconstruct tracks compatible with coordinates of the hit in question. This is achieved through a network which implements a programmable switching system, trained for optimal performance [5].
In this contribution we will show how such a switch is implemented on FPGA and how we can keep the per-event computation time constant at increasing luminosity, by linearly enlarging the system itself, optimising the switch and introducing the concept of input matrices, thus making the architecture desiderable for the future Upgrade II.
References
[1] Real-time track reconstruction with FPGAs in the LHCb Scintillating Fibre Tracker beyond Run 3, ACAT 2024 https://indico.cern.ch/event/1330797/contributions/5796610/
[2] Proposal for FPGA-based tracking in the LHCb downstream region, LHCb-PUB-2024-001, https://cds.cern.ch/record/2888549
[3] LHCb Data Acquisition Enhancement TDR, LHCB-TDR-025, https://cds.cern.ch/record/2886764
[4] Real-time pattern recognition with FPGA at LHCb, an O(n) complexity architecture, CHEP 2024, https://indico.cern.ch/event/1338689/contributions/6015410/
[5] A real-time demonstrator of track reconstruction with FPGAs at LHCb, Connecting The Dots 2023, https://indico.cern.ch/event/1252748/contributions/5521453/
Significance
This is the first public report where it is shown how an optimised managed switch, implemented on FPGA, delivering detector hits to elemental tracking units, in a way that ensures to keep the desired throughput of 30 MHz in high intensity scenarios. This translates in a system whose size (and cost) can scale linearly with the luminosity, thanks to its intrinsic architecture, without relying on time-multiplexing or modifications to the tracking algorithm itself.
| Experiment context, if any | LHCb |
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