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Summary
The simple advantage of 3D vertical integration to an associative memory is obvious – more active silicon per square micron translates to more patterns per chip for a given technology node and chip footprint. This simple view neglects the other significant advantages of 3D, namely the geometric reconfiguration of the basic pattern finding function which leads to power reduction and speed improvement.
The classic pattern recognition associative memory architecture for a single road match consists of a parallel set of CAMs that match hit addresses on a detector layer-for-layer basis combined with an associative function called the Majority Logic that monitors the number of hit matches within the set of CAMs layers. As such in 2D, the more detector layers involved, or the more CAM bits involved per detector layer, the more spread out a single road pattern must be and therefore the longer the interconnect delay of the match and bus lines. It is worth noting that in 2D, large road pattern size and interconnect buses often lead to routing congestion and require “dead” area in the chip, further reducing pattern density. In VIPRAM each single road pattern finding unit has been divided vertically to minimize line delays within a single road that approach or exceed the FO4 delay of the technology node. The net result is a vertical “tube” that represents all the circuitry necessary to recognize one road. The VIPRAM architecture consists of a 2D matrix of these tubes.
The VIPRAM top 3D tier, the Control Tier, contains all of the Majority Logic Cells for each vertical tube or road pattern. Within the top tier, the VIPRAM looks like a binary pixel matrix– a uniform, 2-dimensional array of binary information in which the location of each “true” cell is indicative of which road has been matched. Furthermore, the vertical partition of each road pattern finding unit leads to flexibility of the CAM cell layout itself in which it is possible to optimize the length of the Match Line within the CAM cell to reduce power.
The 3D structure is inherently open and flexible, making possible the design of more general-purpose pattern recognition devices with applications far beyond the original particle physics application.
Vertical Integration has been the subject of a great deal of research and development both within the research community and within the broader VLSI industry. It is viewed by many as the next engine to power Moore’s Law. There are numerous different 3D approaches and techniques. Thus far, for vertical integration with smaller TSV size and larger TSV counts, a major effort in industry has been focused on memory stacking, or CPU and memory stacking – i.e. purely digital circuitry. HEP on the other hand, has concentrated largely on the vertical integration of analog and mixed signal circuitry. VIPRAM is purely digital and technologically close to memory stacking and may very well take full advantages of what has been and will be developed from industry in the near future.
