Speaker
Toshinobu Miyoshi
(KEK)
Description
Monolithic pixel detectors using 0.2 um FD-SOI pixel process have been developed since 2006. An SOI wafer is utilized for sensor and electronics. The top silicon is used for SOI-CMOS circuit, and the substrate is used for a radiation sensor. There is a buried oxide layer between two silicon materials, and these are connected each other through Tungsten via. SOI-CMOS circuit has smaller parasitic capacitance compared with bulk CMOS, and therefore high-speed, low noise and low power circuits can be fabricated. Since a bump bonding is not used, the sensors have high gain with smaller pixel size. Double SOI wafers are also available. In this case, the middle SOI layers are used for shield layer against the back-gate effect and cross talk. When the voltages are applied in the middle layer, the distribution of charge traps caused by radiation in the silicon oxide can be controlled which helps to enhance radiation tolerance. KEK has organized Multi Project Wafer (MPW) runs twice a year and several types of SOI detectors has been developed and evaluated using IR laser and radiation sources. We are also trying to solve existing problems such as sensor-circuit crosstalk and radiation hardness by utilizing double SOI wafers. In this presentation, evaluation test results of up-to-date SOI pixel detectors will be shown.
Primary author
Toshinobu Miyoshi
(KEK)
Co-authors
Ayaki Takeda
(SOKENDAI)
Kazuhiko Hara
(University of Tsukuba (JP))
Mr
Kazuya Tauchi
(KEK)
Shingo Mitsui
(High Energy Accelerator Research Organization (JP))
Shunsuke Honda
(University of Tsukuba (JP))
Dr
Toru Tsuboyama
(KEK, High Energy Accelerator Research Organization)
Yasuo Arai
(High Energy Accelerator Research Organization (JP))
Yoichi Ikegami
(High Energy Accelerator Research Organization (JP))
Yoshinobu Unno
(High Energy Accelerator Research Organization (JP))
Mr
Yowichi Fujita
(KEK)
Yukiko Ikemoto
(KEK)
