Speaker
Description
Summary
Detailed analysis was performed for the folded cascode architecture. Our primary concern was the examination of noise contribution of the devices pair, firstly the input transistor and secondary, the cascoded one. The four structures were: a) nMOS as the input and pMOS as cascode, b) pMOS as input, nMOS as cascode, c) npn as input, pMOS as cascode and d) pMOS as input and npn as cascode. To further isolate these noise contributors, ideal bias current sources and output buffer were used, in all four designs. Feedback was implemented using a capacitance in parallel with a large reset resistor.
In order to achieve a fair comparison, the bias current of the input branch was selected by applying noise-optimisation theory on the input npn available transistor. This bias was then kept constant for the rest implementations, where noise-optimization methodology was applied regarding the input MOS type to set its dimensions. This bias current selection, in addition to constant total power (current) consumption, leads to a constrained bias current for the cascode. This, in the case of the BJT cascode, results to a specific transconductance and parasitic capacitance value, constraining the cascode MOS dimensions in the rest cascode structures.
The output noise was examined in relation to the detector's capacitance variation and the input branch's bias current. In addition, the peaking time dependence (and consequently the operating bandwidth variation) was also examined, concerning the total output noise.
The results of this work aim in proposing input device selection criteria and consequently the folded cascode structure, in relation to the output noise, detector's capacitance variations and the available process (CMOS or SiGe BiCMOS) in conjunction with fabrication cost.
