Speaker
Description
Summary
The NA62 Gigatracker pixel ASIC comprizes an array of 1800 pixel of 300 um each and an End of Column logic on the periphery of the ASIC. The pixel array is stuctured into 40 columns of 45 pixel cells. The pixel circuit comprizes an ultra fast preamplifier and discriminator followed by a differential line driver designed to minimize both digital signal activity and power consumption. The End of Column logic comprizes differential line receivers, banks of TDC's and readout FIFO's that performs derandomisation and data pipeline before to send data off chip.
We present the design aspects of this challenging ASIC architecture, in particular design solutions that have been used to implement subnanosecond circuit in a low power architecture, and the integration of array of TDC's in a front end ASIC, to date the first one implemented.
