Speaker
Description
Summary
The ATLAS CSC system consists of 32 chambers arranged in two endcaps. One chamber consists of four layers, each providing a precision measurement in the radial direction and a coarser measurement of the azimuthal coordinate.
The substantial radiation dose these chambers are expected to accumulate warrants minimal use of highly integrated circuits on the chambers themselves. Processing of digitized data is therefore performed entirely by the off-detector electronics.
The cathode strip signals are amplified, shaped, and the pulse height information stored in switched-capacitor arrays. When triggered, multiple consecutive time samples from all channels are digitized and transmitted off-detector via fiber optic cable.
The off-detector electronics control the sampling and digitization, sparsify the incoming data, organize them into event fragments, and pass them on to data aquisition. Sparsification includes zero suppression, rejection of out-of-time hits, and rejection of background clusters, e.g. from neutrons.
Digital signal processors (DSP) are used for processing the data, while control functions are implemented in FPGAs. One ROD motherboard is shared by 12 DSPs handling a total of two chambers or 1920 channels. Incoming and outgoing fiber optics communications are handled by a separate transition module which connects to the ROD through a custom backplane.
At this time installation of the chambers in ATLAS is complete. We report on details of the implementation, and the performance of the electronics during ATLAS commissioning.
