15–19 Sept 2008
Naxos - GREECE
Europe/Athens timezone

Modular Trigger Processing - The GCT Muon/Quiet bit System and future applications

19 Sept 2008, 10:40
25m
Naxos - GREECE

Naxos - GREECE

Speaker

Mr Matt Stettler (CERN)

Description

The CMS Global Calorimeter Trigger HCAL Muon and Quiet bit processing function is being implemented with a micro TCA system. This system is reconfigurable in both logical functionality and data flow, allowing great flexibility to meet processing requirements. The system consists of a processing module based on a Xilinx Virtex 5 FPGA and custom backplane based on a Mindspeed crosspoint switch. Initial test results of the processing module will be available, and the overall progress of the design will be presented. In addition, future application of this technology for the SLHC level 1 trigger will be discussed.

Summary

This system is being implemented utilizing a multi-gigabit switched serial mesh processing topology. It represents an evolution of the current GCT architecture, taking advantage of the lessons learned implementing the optical data transmission and concentration between the Regional Calorimeter Trigger racks and the GCT leaf cards. This topology is realizable in the micro TCA communications equipment standard, with a custom (though spec compliant) backplane. The core concept is that high speed serial links (both fiber and copper) are used for all communications both internally and externally. Analog crosspoint switching technology is used to provide a flexible communications mesh, allowing a regular hardware topology while retaining significant data routing options. Based on extensive experience with FPGAs in many applications, a concious decision was made to provide plentiful link routing, since connectivity remains the primary limiting factor in fully utilizing the logic resources of large FPGAs.
The processing module provides the data manipulation functionality to implement muon and quiet bit system logic, and directly interfaces to the fiber input from the RCT (through the GCT source cards). It consists of three fiber I/O modules, a Xilinx V5LX110T FPGA, a Mindspeed 21141 crosspoint, and an Ethernet enabled micro controller for slow control.
The processing module hardware will be available in a few months, and initial test results will be presented. Slow control, link testing on the FPGA, and loopback through the crosspoint should be complete.
The backplane provides a combination of star/mesh connectivity, and is based on a Mindspeed 21161 144x144 crosspoint. It is a custom design, but will accept standard uTCA modules. The reason for developing a custom backplane is to provide a level of connectivity unmatched by any currently available commercial unit, a raw capability of 500Gbps will be provided by the design. The backplane design is complete, and updates will be in provided on the layout/fabrication process.
Such a modular design is not only well suited to the GCT muon and quiet bit system, but can also be of use for general trigger processing. The combination of fine grained processing modularity and flexible data routing make it an attractive choice for the trigger upgrades currently being contemplated for SLHC. An initial proposed architecture of the SLHC level 1 trigger based on this technology will be presented.

Primary author

Mr Matt Stettler (CERN)

Co-authors

Dr Costas Foudas (Imperial College) Dr Gregory Iles (Imperial College) Dr John Jones (Princeton University) Mr Magnus Hansen (CERN)

Presentation materials