Speaker
Shingo Mitsui
(High Energy Accelerator Research Organization (JP))
Description
We are developing monolithic pixel detectors using a Silicon-on-Insulator (SOI) technology for X-ray and charged particle applications. It is based on a 0.2 um CMOS fully-depleted (FD-)SOI process of Lapis Semiconductor Co. Ltd. The SOI wafer consists of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits.
To overcome back-gate effect affected by higher back bias voltages, we have successfully introduced buried-well structures. Furthermore, to reduce crosstalk between the sensing node and the pixel circuit, we have developed a double-SOI wafer process. Newly introduced middle Si layer also works as a compensation electrode to the electric field generated by oxide trapped holes created by radiations.
Here we present recent progress and test results of the SOI monolithic pixel detectors.
Author
Shingo Mitsui
(High Energy Accelerator Research Organization (JP))
Co-authors
Akimasa Ishikawa
(Tohoku University (JP))
Ayaki Takeda
(The Graduate University for Advanced Studies (JP))
Kazuhiko Hara
(University of Tsukuba (JP))
Kazuya Tauchi
(High Energy Accelerator Research Organization (JP))
Naoyuki Shinoda
(Tohoku University (JP))
Shunshuke Honda
(University of Tsukuba (JP))
Toru Tsuboyama
(High Energy Accelerator Research Organization (JP))
Toshinobu Miyoshi
(High Energy Accelerator Research Organization (JP))
Yasuo Arai
(High Energy Accelerator Research Organization (JP))
Yoichi Ikegami
(High Energy Accelerator Research Organization (JP))
Yoshimasa Ono
(Tohoku University (JP))
Yoshinobu Unno
(High Energy Accelerator Research Organization (JP))
Yowichi Fujita
(kekHigh Energy Accelerator Research Organization (JP))
Yukiko Ikemoto
(High Energy Accelerator Research Organization (JP))
