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25–29 Sept 2015
International Conference Center (also named as <a href="http://www.jdnyhotel.com/index.php" target="_blank">“Nanyang Hotel”</a>)
PRC timezone

Radiation-Hard/High-Speed Parallel Optical Engine

28 Sept 2015, 09:50
20m
International Hall (International Conference Center (Nanyang Hotel))

International Hall

International Conference Center (Nanyang Hotel)

Speaker

K.K. Gan (The Ohio State University (US))

Description

The LHC at CERN is now the highest energy and luminosity collider in the world. The collider and detectors have just completed an upgrade to operate at higher energy and luminosity. In addition, there are plans to further upgrade the collider and detectors to operate at even higher energy and luminosity. This requires the optical links to transmit data at much higher speed to handle the much increased luminosity. We will present the results from the just completed optical link upgrade for the pixel detector of the ATLAS experiment and the future R&D project. For the completed upgrade, we designed and produced new radiation-hard/high-speed parallel optical engine for the upgraded pixel detector. The new fiber optic transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed on the ATLAS pixel detector and for the new pixel layer. Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver/driver ASICs. The new opto-board design benefits from the first generation production and operational experience and contains several improvements. The new opto-boards have been installed. We will present the design, production and operational experience, and reliability study of the new opto-boards. For the future upgrade, we design an ASIC that contains an array of 4 high-speed/radiation-hard drivers to operate an array of 4 VCSELs (Vertical Cavity Surface Emitting Lasers). The bandwidth of each driver is 10 Gb/s. The plan is to increase the number of channels to 12 channels. With the spacing of 250 μm between two VCSELs, the width of an optical array is only 3 mm. This allows the deployment of a compact 120 Gb/s parallel optical engines at a high radiation location close to the interaction region where space is at a premium. We will present the result from the 4-channel driver ASIC fabricated with 65 nm CMOS process. We have also designed a new opto-board that couples the ASIC to an VCSEL array. The result from the new high-speed optical engine will be presented together with the future plans.

Primary author

K.K. Gan (The Ohio State University (US))

Presentation materials