Speaker
Description
Summary
A monolithic active pixel sensor for the upgrade of the ALICE Inner Tracking System [1] is being developed in the TowerJazz 180 nm CMOS imaging Sensor process [2] wich offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials.
To limit material budget, power consumption should not exceed 100 mW/cm2. The collected charge over input capacitance (Q/C) ratio determines analog power consumption. Varying sensor geometry and applying reverse bias yields an input capacitance of around 2.5 fF [3] and a Q/C for an 18 μm epitaxial layer of about 80 mV distributed over a few pixels in a cluster. This allowed the implementation of a ~40nW open-loop binary charge sensitive front end with minimum charge threshold below 100 electrons. A front end peaking time of a few μs allows it to function as a memory: a strobe or trigger with this latency can be applied to latch hit information. A first large-scale prototype fully satisfies ALICE requirements [4]. Measurements revealed an ENC of only a few electrons, but a threshold spread of 18 electrons RMS much larger than simulations predicted. Better channel-to-channel uniformity of charge threshold and time response, intimately related, would further improve operating margins. An in-depth optimization of the front end was carried out: 8 different sectors of 65536 pixels each are equipped with a different version of the pixel gradually introducing various changes to the front end and sensor expected to improve uniformity. These include resizing certain transistors, modification of the circuit including the part to clip large signals, and the introduction of local protection diodes for gates of bias transistors as this was observed to improve matching in other projects [5] even if antenna rules were respected without them.
This third full-scale ALPIDE prototype is being submitted for fabrication now. It is also the first one to include a 1.2 Gb/s data transmission unit. With the 40nW front end, analog power consumption on the full chip is about 5 mW/cm2. Total power consumption is expected to be about 40 mW/cm2, dominated by digital circuitry and the data transmission unit. Further power optimization is planned as part of the R&D towards a production-ready prototype at the end of this year. The paper will present relevant measurement results on the present prototypes, the front-end design optimization, and hopefully first measurement results on the new full-scale prototype.
References
[1] L. Musa et al., CERN-LHCC-2012-013. LHCC-P-005, CERN, Geneva (2012). http://cds.cern.ch/record/1431539?ln=en
[2] S. Senyukov et al.,
http://dx.doi.org/10.1016/j.nima.2013.03.017
[3] J. Van Hoorne et al., https://indico.cern.ch/event/192695/session/7/contribution/284
[4] Y. Ping et al., JINST 10 C03030, http://dx.doi.org/10.1088/1748-0221/10/03/C03030
[5] R. Ballabriga,
https://indico.cern.ch/event/228972/session/16/contribution/224
