Speaker
Description
The ATLAS detector at the LHC is in the process of integrating new components to handle the increased collision energies and luminosities being delivered since 2015. The Fast TracKer (FTK) is a hardware processor built to reconstruct tracks at a rate of up to 100 kHz and provide them to the high level trigger. FTK uses FPGA's to match inner detector hits with pre-defined track patterns stored in associative memory on custom ASICs. This presentation describes the electronics facilitating FTK’s massive parallelization alongside the planned installation and commissioning of the system during 2016.
Summary
From 2010 to 2012 the Large Hadron Collider (LHC) operated at a centre-of-mass energy of 7 TeV and 8 TeV, colliding bunches of particles every 50 ns. During operation, the ATLAS trigger system performed efficiently contributing to important results, including the discovery of the Higgs boson in 2012. The LHC restarted in 2015 and will operate for four years at a centre-of-mass energy of 13 TeV and 14 TeV with bunch crossings every 25ns. These running conditions result in the mean number of overlapping proton-proton interactions per bunch crossing increasing from 20 to 50. The Fast TracKer (FTK) will allow the trigger to utilize tracking information from the entire detector at an earlier event selection stage than ever before,
enabling more efficient event rejection.
The FTK is designed to perform full scan track reconstruction of every event accepted by the ATLAS first level hardware trigger. To achieve this goal the system
uses a parallel architecture, with algorithms designed to exploit the computing power of custom Associative Memory chips and modern field programmable gate arrays. The processor will provide computing power to reconstruct tracks with transverse momentum greater than 1 GeV in the whole tracking volume. The tracks will be available at the beginning of the trigger selection process, facilitating the development of more pileup resilient triggering strategies. The Fast Tracker system will be extremely large, with about 8000 Associative Memory chips and 2000 field
programmable gate arrays, providing full tracking with a rate up to 100 KHz and an average latency below 100 microseconds. The system will begin commissioning in 2016, with full barrel coverage reached by the end of the year. We present the final version of the electronics, with details covering the hardware status and installation of the system. An overview of the commissioning status and first data-taking experience will also be presented.
