TWEPP 2016 - Topical Workshop on Electronics for Particle Physics

Session

Plenary

30 Sept 2016, 09:00

Tulla Lecture Hall (Building 11.40) (Karlsruhe Institute of Technology (KIT))

Conveners

Plenary: Trigger

• Julie Whitmore (Fermi National Accelerator Lab. (US))

Plenary: ASIC

• Alessandro Marchioro (CERN)

Plenary: ASIC

• Alessandro Marchioro (CERN)

70. The CMS Level-1 Calorimeter Trigger for LHC Run II

Alexandre Zabi (Centre National de la Recherche Scientifique (FR))

30/09/2016, 09:00

Trigger

Oral

Results from the completed Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed in two stages, with the first running in 2015 for pp and Heavy Ions and the final stage for 2016 data-taking. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Stages of the upgrade were commissioned in parallel with...

72. Installation, Commissioning, and Running of the ATLAS Fast Tracker Hardware System

Nikolina Ilic (Stanford University (US))

30/09/2016, 09:25

Trigger

Oral

The ATLAS detector at the LHC is in the process of integrating new components to handle the increased collision energies and luminosities being delivered since 2015. The Fast TracKer (FTK) is a hardware processor built to reconstruct tracks at a rate of up to 100 kHz and provide them to the high level trigger. FTK uses FPGA's to match inner detector hits with pre-defined track patterns stored...

21. TOFFEE: a fully custom amplifier-comparator chip for timing applications with silicon detectors.

Francesca Cenna (Universita e INFN Torino (IT))

30/09/2016, 09:50

ASIC

Oral

In this contribution we present the design of a 8-channel amplifier-comparator chip specifically optimized to match the signals produced by Ultra-Fast Silicon Detectors (UFSD). The time resolution of the TOFFEE – UFSD system is expected to be around 30 ps. The chip is designed in UMC 110nm CMOS technology, it has a 2x2 mm area and it requires 40 mW per channel. It features LVDS outputs and...

12. The VeloPix ASIC

Tuomas Sakari Poikela (CERN)

30/09/2016, 10:15

ASIC

Oral

The LHCb upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in triggerless mode, with full event selection being performed offline. The Vertex Locator (VELO) will be upgraded to a pixel device with a new dedicated ASIC, the VeloPix, a 130 nm technology chip with data driven and zero suppressed readout. The sensors are positione at just 5.1 mm from the LHC...

71. AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

Valentino Liberali (Università degli Studi e INFN Milano (IT))

30/09/2016, 11:10

ASIC

Oral

This paper describes the AM06 chip, a highly parallel processor for
pattern recognition in high energy physics. AM06 contains memory banks
that store up to 2^17 patterns made up of 8x18 bit words and integrates
SER/DES IP blocks for 2.4 Gb/s IO to avoid routing congestion.
AM06 combines custom memory arrays, standard logic cells and IP blocks
within a 168 mm^2 silicon area with 421 million...

4. Rad-hard DCDC converters for HL-LHC experiment's tracker modules power distribution

Giacomo Ripamonti (CERN, Ecole Polytechnique Federale de Lausanne (CH))

30/09/2016, 11:35

ASIC

Oral

In the context of investigating a more efficient rad-hard power distribution scheme for HL-LHC trackers modules based on switching DC/DC converters, we developed two new prototypes, upFEAST2 and DCDC2S. The combination of upFEAST2 and two DCDC2S can provide the three required voltages (2.5V for the opto-electronics, 1V for digital and 1.2V for analog circuitry).
DCDC2S and upFEAST2 are...