Speaker
Description
Summary
CMOS Monolithic Active Pixel Sensors (MAPS) are characterized by their detection efficiency close to 100 %, high granularity (~µm), fast read-out frequency (~k frame/s), low material budget (~30 µm Si) and radiation tolerance (~1 Mrad, ~10e13 neq/cm2). They are foreseen to equip new generation vertex detectors in subatomic physics experiments. Their first application coincides with the upgrade of the Heavy Flavor Tracker (HFT) in the STAR (Solenoidal Tracker at RHIC) experiment. They will also equip the beam telescope of the European project: EUDET. Both of these two applications need sensors with digital output and with integrated zero suppression circuit in order to increase the read-out frequency per frame with the aim to reduce the frame occupancy.
The zero suppression circuit integrated in a CMOS pixel sensor is located at the bottom of a matrix and after an analogue to digital conversion circuit. Mimosa26 designed for the EUDET telescope, implements such architecture. It consists of a pixel array of 576 row and 1152 columns with a pixel pitch of 18.4 µm. Each pixel includes an amplification and a Correlated Double Sampling (CDS). The sensor is read out in a rolling shutter mode, each column of pixels ends with a discriminator performing the analogue to digital conversion. The data from 1152 discriminators are processed by the zero suppression circuit.
Before its integration into a final sensor, the concept of the zero suppression logic has been validated. SUZE-01, a reduced scale, fully digital circuit, able to treat and format 128 emulated discriminator outputs, has been successfully fabricated and tested in 2007. The test shows that the algorithm of hits pixel selection is fully operational. This concept is now implemented into the Mimosa26 chip. The zero suppression circuit is structured in a 3 stage pipeline. In the first stage, the 1152 discriminator outputs will be distributed over 18 parallel banks, where a sparse data scan algorithm on hit pixels is performed. Up to 4 contiguous pixel signals above threshold (string) will be encoded in a 2 bit state word. Up to N states per bank can be memorised with column addresses. The column address of a string shared by two neighbouring banks will be transferred only once. The second stage will combine the outcomes of the 18 banks of the first stage. Its multiplexing logic accepts up to M states per pixel row and adds bank address information. N and M will respectively be equal to 6 and 9, according to the hit density defined by the estimated (simulated) amount of events. These values are taking into account a safety margin for the EUDET telescope. The results of the second stage will be stored in the third stage, i.e. a 96 kbit memory split in 2 buffers, allowing a continuous read-out via one or two LVDS links at up to 100 MHz.
The contribution to the workshop includes a description of different steps of the architecture. The validation tests of Mimosa26 will also be presented.
