Speaker
Description
The NA62 experiment at CERN SPS is aimed at measuring the branching ratio of the ultra-rare K+→π+νν decay.
This imposes very tight requirements on the particle identification capabilities of the apparatus in order to reject the considerable background.
To this purpose a centralized level 0 hardware trigger system (L0TP) processes in real-time the streams of data primitives coming from the detectors readout boards.
Our approach aims at improving the L0TP performances distributing this processing over the whole chain starting from the earliest stages, i.e. the readout boards, and operating on the data streams with an orchestrated combination of heterogeneous computing devices (CPUs, FPGAs and GPUs).
The key element of this real-time distributed stream computing architecture is NaNet, a FPGA-based PCI Express Network Interface Card with processing, RDMA and GPUDirect capabilities, supporting multiple link technologies (1/10/40GbE and custom ones).
We have demonstrated the effectiveness of our method by harvesting the computing power of latest generations nVIDIA Pascal and Volta GPUs and of the FPGA hosted by NaNet to build in real-time refined physics-related primitives for the RICH detector, as the knowledge of Cerenkov rings parameters allows building more stringent conditions for data selection at low trigger level.
Recent results collected during NA62 runs along with a detailed description of the latest developments in the NaNet architecture and an insight of future project developments are presented and discussed.
