Speaker
Description
We present the latest results of the FE65-P2 pixel readout test chip. This is a 64 by 64 pixel matrix on 50 um by 50 um pitch, produced in 65nm CMOS technology at the end of 2015. FE65-P2 was designed to demonstrate small pixel performance and stable operation down to 500 electron threshold even with the front end pixel amplifiers embedded in a synthesized logic environment. The FE65-P2 results inform the ongoing design of a large format (400 by 192 pixels) demonstrator readout chip to be produced by the RD53 collaboration in mid 2017.
Summary
FE65-P2 makes use of layout scheme dubbed "analog islands in a digital sea", where each set of four analog front ends (analog quad) is fully surrounded by synthesized logic, which is not a step and repeat layout, leading to a slightly different environment around each analog quad. A comprehensive substrate isolation strategy was used to achieve the required low stable threshold and excellent uniformity. FE65-P2 chips are being bump bonded to miniature matching sensors to allow full module performance studies. Test results will be presented including irradiation and beam tests. This work is carried out in the context of the RD53 collaboration, which is developing the pixel readout technology to cope with the high rate and radiation together with low noise and low power requirements for the High Luminosity LHC upgrades of the ATLAS and CMS experiments.
