Speaker
Description
The SSA is a silicon-strip readout ASIC for the hybrid Pixel-Strip detector of the CMS Outer Tracker High Luminosity LHC (HL-LHC) Phase II upgrade. It is a 120-channel ASIC with double-threshold binary readout architecture, utilizing a quick hit cluster finding logic to provide encoded hit information for particle momentum discrimination to the Macro Pixel ASIC (MPA) at the bunch crossing rate of 40MHz, while allowing the full sensor readout at a nominal average trigger rate of 750KHz.
The design and the implementation in a 65nm CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation will be presented in this paper.
Summary
The Compact Muon Solenoid experiment at CERN is foreseen to receive a substantial upgrade of the outer tracker detector and its front-end readout electronics, requiring higher granularity and readout bandwidth to handle the large number of pileup events in the High-Luminosity LHC. For this reason, the entire tracking system will be replaced with new detectors featuring higher radiation tolerance and ability to handle higher data rates and readout bandwidths. The possibility of identify particles with high transverse momentum to provide primitives for the L1 trigger decision, requires the adoption of double layer sensor modules and the development of two different front-end ASICs: the Short Strip ASIC (SSA) and the Macro-Pixel ASIC (MPA) allowing to reduce the total output data flow from 1.3Tbps to 30Gbps per module while limiting the total power density below 100mW/cm2 .
The SSA is the front-end ASIC responsible of reading-out the Short-Strip silicon sensor and to provide encoded information for the particle momentum discrimination. It is implemented in a 65nm CMOS technology utilizing 8 metal layers and is bump bonded to a flex hybrid. A total of 85000 SSA ASICs will be used in the CMS outer-tracker.
The analog front-end channel is composed by a regulated cascode pre-amp coupled to a booster amplifier followed by a double threshold folded cascode discriminator circuit capable to distinguish between hits with an energy over the minimum ionizing particle energy and high ionizing particles (HIPs). A single ended architecture of the input stage is optimal from the point of view of demanding requirements for the noise performance (ENC<1,000e-) and power consumption (<220μA per channel).
A digital back-end circuit processes the discriminated hits and generates the trigger data and the L1-accept readout data streams. The discriminator pulses are sampled at the bunch crossing rate and follow two distinct data paths: the trigger data path and the L1 data path. The first consists of a strip clustering logic that calculates the centroid position of the hit clusters, encode the information and apply a parallax correction. The encoded hits are transmitted with a bandwidth of 2.88 Gbps to the MPA ASIC for correlation with pixel sensor hits. In the L1 data path, the full sensor hit array is stored in a rad-hard static RAM waiting for the arrival of a Level-1 trigger. Up to 24 High Ionizing Particles hits (HIPs) flags are transmitted along the full short-strip sensor image.
For the design implementation, a fully scripted Digital-On-Top flip-chip methodology is used. Special attention was given in the use of radiation tolerant techniques in order to mitigate the effects of Single Event Upsets in the digital control circuitry, while maintaining low power consumption. Radiation hardening techniques have also been adopted in the analog front-end circuits to guarantee operation up to a target Total Ionizing Dose of 100Mrad.
We will present the design architecture and the development work of the first prototype SSA ASIC integrating all required functionalities for system level operation. The design will be submitted for prototyping in a common full mask set 65nm engineering run along with the MPA ASIC.
