Speaker
Description
High-performance analog-to-digital converters (ADCs) are becoming essential
building blocks in many applications including optical communications, high-speed test
equipment such as real-time oscilloscopes, and high-energy particle physics, etc. While several ADC architectures have been proposed, SAR (Successive Approximation Register) has become the de facto preferred design, because of its low power, small silicon area, and scalability with advanced CMOS technologies. Time-interleaving architecture is a promising way to further improve the conversion rate in a given technology and push it to 100GS/s. This talk will give an overview of high-speed time-interleaved SAR ADC design, the working principle, design challenges and possible solutions. In the end, a 64 GS/s 8-bit time-interleaved ADC implemented in a 28 nm CMOS process will be presented as an example, including the proposed design techniques, calibration methods, and silicon measurement results.
