Speakers
Description
We developed a front-end ASIC for a CdTe pixel detector as a part of a R&D effort toward advanced hard X-ray or gamma-ray imaging devices for applications in a variety of fields such as astronomy, medical research and non-destructive analysis. The ASIC is designed for a hybrid configuration where each CdTe pixel can be vertically bump-bonded to a corresponding pixel circuit. The chip consists of 28-by-28 identical cells of 250um-by-250um in silicon area, and is implemented with TMSC 0.35-um CMOS technology. The signals are acquired either in the peak-hold or sample-hold mode before being fed into a column-parallel A-to-D converter. We tested circuit performance and confirmed that its equivalent noise charge was 40 electrons, its integral non-linearity about 1%, and the power consumption 0.2mW per pixel.
