Jul 4 – 11, 2018
COEX, SEOUL
Asia/Seoul timezone

Progress on the 650MHz/800kW CW klystron development at IHEP

Jul 5, 2018, 3:00 PM
30m
205 (COEX, Seoul)

205

COEX, Seoul

Parallel Accelerator: Physics, Performance, and R&D for Future Facilities Accelerators: Physics, Performance, and R&D for Future Facilities

Speaker

Shengchang Wang (IHEP)

Description

The configurations of the CEPC and the SPPC were proposed in September, 2012. To reduce the costs of the construction and the operation, high efficiency klystrons is preferred for the Collider ring. In this scenario, the plan to develop the high efficiency 650MHz/800kW CW klystron with an ultimate goal of 80% is initialized. Since there are no any experiences and infrastructures such as the large baking furnace and the high power testing stand to develop these kind of high power CW klystrons in China, the 1st klystron prototype is based on the conventional 2nd harmonic bunching technology, then more klystron prototypes will be made with steady improvement of the efficiency. In this paper, the progress on the 1st 650MHz/800kW CW klystron prototype development at IHEP is presented. Till now, the mechanical design of the 1st klystron prototype has been finished; the fabrication will be started soon. In addition, the design of the 2nd klystron prototype and the strategic plan to progressively increase the klystron efficiency will also be shown.

Primary authors

Presentation materials