Speaker
Description
Extreme miniaturization of packages and high-density interconnects are routinely demanded by many HEP applications. The following challenges are key to satisfy these demands:
- How to build smallest (volume, foot-print and weight) systems (Miniaturization)
- How to decrease the die spacing in-between individual sensor (Placement accuracy)
- How to integrate optical data transmission systems (Miniaturization/Placement accuracy)
- How to better dissipate heat (Thermal management)
- How to mix technologies (Hybrid)
This overview covers many aspects of packaging technologies suitable for such constraints, such as:
- Taiko wafer thinning
- bumped wafer thinning technologies
- wafer bumping with or without redistribution layers (RDL)
- Fan-out technologies
- laser, stealth or DRIRE dicing methods
- flip-chip technologies
- multi-layer flex circuit with micro-via
- glass and silicon interposers, 3D packaging.
This presentation aims to give an overview in term of technology maturity level and reliability concerns.
