Because of its radiation resilience, p-type silicon has been established as baseline material for tracking detectors in upcoming high-luminosity physics experiments. When deciding on the quality of p-type silicon strip sensors, strip isolation is crucial. Regions of highly doped p+ implant (p-stop) are introduced between n+ strips to interrupt the electron accumulation layer that forms at the interface to the overlying oxide. Doping concentration, implantation depth and geometry of the p-stop regions determine the achieved inter-strip resistance. Typically, inter-strip resistance is measured directly on the strip sensors. The measurement, however, is prone to substantial errors. Large resistances on the order of 100 GΩ require precise, low-noise measurement setups, which are influenced strongly by parasitic currents.
To provide a comparably simple alternative to measurements on strip sensors, this contribution aims to relate the threshold voltage and inter-channel resistance of field effect transistors (FET) to the inter-strip resistance of silicon strip sensors. We compare measurements of dedicated test structures to measurements on strip sensors with different n- and p-spray implantations and present comparative TCAD simulations. The FET test structures could present a fast and reliable option to judge inter-strip resistance and strip isolation properties on silicon sensors. This would be especially valuable for process quality control during future series productions.