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How to do ultrafast Deep Neural Network inference on FPGAs

6 February 2019
University of Zurich, Campus Irchel
Europe/Zurich timezone

Thea Årrestad

Contribution List

7 out of 7 displayed
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  1. 6. Registration
    06/02/2019, 08:30
  2. 5. Welcome
    Thea Aarrestad (Universitaet Zuerich (CH))
    06/02/2019, 09:00
  3. 1. What is HLS4ML?
    Jennifer Ngadiuba (CERN)
    06/02/2019, 09:15

    An introduction to the HLS4ML framework

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  4. 4. Firmware implementation with SDAccel
    06/02/2019, 11:00

    Export HLS design to firmware with Xilinx SDAccel on Amazon cloud.

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  5. 2. Optimize FPGA design: quantization and parallelization with HLS4ML
    Jennifer Ngadiuba (CERN)
    06/02/2019, 13:30
  6. 7. Optimize FPGA design: model compression
    06/02/2019, 14:30
  7. 3. Model acceleration on cloud FPGAs
    Jennifer Ngadiuba (CERN)
    06/02/2019, 16:00