CMOS Pixel Sensors (CPS) are attractive for CEPC vertex detector construction due to its high granularity, high speed, low material budgets, low power and potential high radiation tolerance. For the innermost layer of CEPC vertex detector, the expected resolution is 3 to 5 μm; the bunch spacing of CEPC vertex detector is 680 ns for Higgs, 210 ns for W and 25 ns for Z; the hit density is...
The CIS115 is a Teledyne-e2v CMOS image sensor with 1504 x 2000 pixels of 7 µm pitch. It has a high optical quantum efficiency owing to a multi-layer anti-reflective coating and its back-side illuminated construction, and low dark current due to its pinned photodiode 4T pixel architecture. The sensor operates in rolling shutter mode with a frame rate of up to 7.5 fps (if using the whole...
This work presents the design and implementation details of a 64 × 64 pixel readout circuit designed at AGH UST. The analog front-end [1] is based on an inverter amplifier and uses a novel feedback topology, which allows for very short pulse-shaping times, while maintaining good gain linearity. Fine pixel pitch of 50 µm requires certain measures for charge sharing compensation. For that...
Hybrid Photon Counting (HPC) detectors revolutionized measurement methods and data collection strategies at synchrotron facilities and laboratories over the last 10 years thanks to key features such as the absence of readout noise, high photon flux capability, high dynamic range and high frame-rate. Similar advantages are expected to be directly transposed to the field of electron detection,...
ATLAS is one of the four major experiments at the Large Hadron Collider (LHC) at CERN. The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, located at the core the ATLAS tracker.
During operation at instantaneous luminosities of up to 2 10^34/cm^2/s the
frontend chips of the ATLAS innermost pixel layer (IBL) experienced single
event upsets...
Read-out electronics for High-Energy Physics Experiments as for example Compressed Baryonic Batter experiment at FAIR, Darmstadt, Germany, should meet tight requirements concerning noise (ENC < 1000 e- rms to guarantee proper measurements of charge), power consumption (< 10 mW/ channel) and high average input hit frequency (250 kHit/s/channel) [1]. The ICs design should take into account not...
