Speaker
Description
Results from the Phase 1 Upgrade of the CMS Level-1 Calorimeter Trigger are presented. The upgrade was completed before the 2016 data-taking and the system served until end of Run II in 2018. The hardware uses Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links and operates in microTCA chassis. Innovations are introduced, such as embedded linux on trigger processing boards and simultaneous eye-scans on data links. The final stage architecture is time-multiplexed. The focus will be on calorimeter trigger algorithm design and their firmware implementation. Precise FPGA floorplanning allows placing of all calorimeter trigger algorithms in a single board.
Summary
The LHC has resumed operations since the spring of 2015. During Run II, the instantaneous luminosity is already exceeding the design parameters of the machine. To maintain acceptance for proton and heavy ion collision events of interest without exceeding the 100 kHz limit, the CMS Level-1 (L1) trigger has been upgraded. The L1 calorimeter trigger, which finds electrons, photons, tau leptons, jet candidates and computes energy sums, has been upgraded. In these intense conditions, dedicated pile-up mitigation techniques have been implemented in order to reach acceptable performance. Modern technologies offer an effective solution to achieve these goals. The upgraded system makes use of new Xilinx Virtex-7 based AMC cards form the microTCA technology.
The final stage of the upgraded architecture implements an innovative approach called the Time-Multiplexed-Trigger (TMT). Higher granularity inputs, algorithms operating on a wider field of view allow for improved position and energy resolution of regional and global quantities. Calorimeter trigger primitive data is transmitted on 1,152 optical links running at either 4.8 Gbps or 6.4 Gbps. This is pre-processed at Layer-1 before being time multiplexed to Layer-2 where each node processes data from the entire calorimeter. Optical interconnects are via 10 Gbps optical links, which allow easy reconfiguration or expansion as required. This has been made substantially easier with the early adoption of Molex Flexplane technology. Data is then de-multiplexed before sequential transmission to the Global Trigger.
Calorimeter Trigger Processor, Virtex-7 (CTP7) AMC cards serve as the Layer-1 pre-processors, and MP7s serve as the Layer-2 Master Processor nodes. This approach is designed to allow for a high processing clock speed of 240 MHz and thus efficient use of logic resources. The fully pipelined firmware approach of the TMT provides an efficient way to localize the processing, reduce the size and number of fan-outs, minimize routing delays and eliminates register duplication. All calorimeter object algorithms are placed and routed into a single board using a precise FPGA floorplanning. The High Level Trigger model inspired the design of the upgraded Level-1 system.
The poster will cover the technological aspects of the Run II calorimeter trigger system emphasizing the many challenges of its implementation and in particular the innovative algorithms proposed. Results of its performance during the 2016–2018 data taking of proton collisions of the LHC will be presented and used to illustrate the experience gained in terms of implementation of complex electronics systems for triggering in HEP. These systems are now used as a baseline for future trigger design. They also rely on the deployment of high-speed optical links and large FPGA processing. The AMC boards designed for this project are aiming towards a standardization of the data processing required for the future LHC electronics systems.
