Sep 20 – 24, 2010
Aachen, Germany
Europe/Zurich timezone

Subnano Time to Digital Converter implemented in PARISROC_V2 for PMm² R&D program

Sep 23, 2010, 4:00 PM
2h
Aula

Aula

Poster ASICs POSTERS Session

Speaker

Mr Sebastien Drouet (Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11)

Description

PARISROC_V2 is a complete read out chip, in AMS SiGe 0.35µm technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and its belongs to an R&D program funded by the French national agency for research (ANR) called PMm²: “Innovative Electronics for photodetectors array used in High Energy Physics and Astroparticles”. The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a 10-bit Wilkinson ADC and a 24-bit counter. The time measurement is made by 2 complementary systems: a 24-bit gray counter (coarse time) with a step of 100ns, and a double ramp TDC (fine time) with a 10-bit resolution and a precision less than 1 ns. It is interesting to underline the fact that the double ramp generator is common to all channels. The poster presents the TDC architecture and the first fine time measurements.

Primary authors

Mr Eric Wanlin (Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11) Mr Sebastien Drouet (Institut de physique nucleaire d’Orsay – CNRS-IN2P3/Universite Paris 11)

Presentation materials