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Overview
The organizers of Real Time 2024 are pleased to offer a two-day pre-conference program that will focus on several valuable open-source tools that support development of FPGA applications and custom ASIC designs. This workshop will be held on Saturday and Sunday (April 20-21) and will cover the general topics described below.
More details will be provided here as the program is being developed. If you have questions about this workshop please contact Marc-André Tétrault
General day schedule (Saturday and Sunday)
8:15 ~ Bus leaving the Seagull Hotel for ICISE (please arrive ahead of time)
8:30-9:00 ~ Arriving at ICISE, getting the virtual machine working.
9:00-12:30 ~ Morning workshop (presentation, hands-on exercises and breaks)
12:30-13:30 ~ Lunch
13:30-17:00 ~ Afternoon workshop (presentation, hands-on exercises and breaks)
17:00-17:30 ~ Wrap-up and return to hotel
Part 1 - Cocotb
Trainer: Marc-André Tétrault, Université de Sherbrooke
FPGA and ASIC technology are one of the many critical components in nuclear science instrumentation, with their complexity increasing significantly over the years. Both permanent ASIC and reprogrammable FPGA digital designs require exhaustive test benches to verify and improve the real-time systems they implement, where HDL languages (Verilog or VHDL) usually require a long ramp-up to expertly use. Open-source tools have appeared and matured in recent years, including the Python-based Cocotb package, accessible to a much broader range of students and scientists. This alternative avenue further provides access to broader code-reuse opportunities, as Python is heavily used in our community.
The first part of the open-source workshop for real-time systems will introduce this modern verification language, concepts of functional verification and of functional coverage. Participants will build a simple, customized Python-based interface between the test bench and FPGA pins. The driver will then be structured in a Python class to implement a basic but highly reusable verification environment. The hands-on exercise will end with an existing, open-source driver which targets the AXI bus, which can be paired with many vendor IPs modules, as well as community IPs presented in the second part of this workshop. Lastly, the session will conclude with contrasts against what is available in some commercial tools and their supported verification methodologies.
Presentation, contains link to lab materials:
Part 2 - SURF
Trainer : Larry Ruckman, SLAC National Accelerator Laboratory
The SLAC Ultimate RTL Framework (SURF) is a firmware framework that has been developed by SLAC National Accelerator Laboratory. It is a substantial VHDL library, built upon more than 10 years of development. It finds extensive utilization in AMD/Xilinx FPGAs and custom digital ASIC designs. The framework comprises VHDL-based intellectual properties (IPs) for commonly implemented modules. It has been widely adopted by numerous experiments and applications. SURF is open source and published on Github.
The initial segment of this SURF workshop will feature an introductory session delving into the coding philosophy that serves as its foundation. Participants will learn how to effectively navigate through SURF's code organization and understand the various software dependencies that can be leveraged to maximize the advantages offered by this firmware library. In the practical exercise, attendees will have the opportunity to run cocotb-based demonstration simulation scenarios and create a personalized AXI-Lite endpoint, which will both be simulated using readily available open source simulation tools. Finally, to wrap up the session, a collection of finished examples showcasing firmware and software projects will be shared. These examples can serve as valuable templates for initiating custom projects of your own. Prior experience with VHDL, Python, virtual machines, and Linux is highly recommended for this section of the workshop.
Links to presentation, contains links to lab materials.
Part 3 – FABulous eFPGAs
Trainers: Nguyen Dao, Dirk Kock, Heidelberg University
This workshop introduces the versatile and customizable FABulous framework for generating embedded FPGAs ( eFPGAs). The framework is entirely open and deals with the ASIC generation, bitstream generation of user logic circuits (to be executed on the fabric) as well as with the simulation/emulation of fabrics.
In the first part, attendees will learn about FPGA basics (as relevant for implementing own FPGAs), basic FABulous concepts, and how to integrate prebuilt FPGA tiles into an FPGA fabric that can later be integrated as a macro into your own designs. We will also cover how the Verilog (or VHDL) to bitstream compilation path is generated for customized fabrics.
In a second part, we show how custom primitives (e.g., your special ML acceleration or crypto primitive) can be integrated into your own fabric and how the routing fabric of the eFPGA or I/Os can be tailored to specific needs.
In a small lab, attendees will specify a custom eFPGA, compile it and compile a bitstream for that fabric. Moreover, we will explore important design files to gain a deeper understanding of the operation of FABulous. Finally, we will add a new custom DSP block and modify the routing fabric to incorporate that block.
Links to presentation and lab materials:
First slide deck
Hands-on tutorial
Physical Implementation by Nguyen
Source files (link upcoming)
Part 4 - Open-source ASIC Design (openLANE, Skywater, Caravel)
Trainers: Carl Grace, Tarun Prakash, Lawrence Berkeley National Laboratory
This interactive workshop provides an introduction to the efabless openLANE design flow and the Skywater 130nm open Process Design Kit (PDK) for ASIC design , as well as the efabless Caravel “harness” SoC. Its objective is to explore the transformative potential of open-source tools in ASIC design, revolutionizing the understanding and approach to this field. Throughout the workshop, participants will gain insights into the different stages of the design process, acquiring a comprehensive understanding of the entire ASIC design flow.
The workshop focuses on enabling participants to perform a complete RTL to GDSII flow, covering synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis. It incorporates hands-on exercises and practical examples to ensure participants can delve deeply into each step of the design flow, facilitating a holistic understanding of the process. Furthermore, participants will have the chance to acquaint themselves with the efabless Caravel “harness” SoC, a convenient and user-friendly tool that enables them to effortlessly incorporate their custom design with a verified processor-enabled template (the harness) and create tapeout-ready chips. This ready-to-use harness simplifies the process, allowing participants to seamlessly proceed with chip fabrication.
By the end of the workshop, participants will have obtained invaluable experience and practical knowledge in utilizing open-source tools for ASIC design. They will be equipped with foundational skills to navigate the intricate landscape of modern chip design using the efabless openLANE design flow and the Skywater 130nm open PDK.
