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24th IEEE Real Time Conference - ICISE, Quy Nhon, Vietnam
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Description
24th IEEE Real Time Conference
ICISE, Quy Nhon, Vietnam
April 22-26, 2024
A big thank you to all particpants for your contributions to a successfull conference. We look forward to seeing everyone again in Elba, Italy (May 25-29, 2026)
Women in Engineering Event
A special event connecting, supporting and inspiring women in science and engineering will be held on Tuesday, April 23, 19:00 at Seagull Hotel. Everyone is cordially invited to join for short presentations and a panel discussion as well as a networking get-together (with food and drink!).
Read more about the Women in Engineering event HERE
Like the previous editions, RT2024 will be a multidisciplinary conference devoted to the latest developments on real time techniques in the fields of plasma and nuclear fusion, particle physics, nuclear physics and astrophysics, space science, accelerators, medical physics, nuclear power instrumentation and other radiation instrumentation.
The conference will provide an opportunity for scientists, engineers, and students from all over the world to share the latest research and developments. This event also attracts relevant industries, integrating a broad spectrum of computing applications and technology.
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09:00
Lunch
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Welcome, Invited Talk, Orals presentations
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10:00
Welcome
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1
Invited Talk: High performance CdTe base imaging-spectrometers for space-science and societal applicationsSpeaker: Olivier Limousin (CEA/DRF/IrfuDAp)
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2
AMBER experiment's online filter system for virtualised IT infrastructure
High-energy physics experiments require significant computing resources to operate their high-level trigger systems. Typically, these systems are constructed as extensive computing farms with cutting-edge expensive hardware to provide sufficient computing power. Usually located on-site, these systems process detector data in real time and minimize their latency. In this paper, we present an alternative high-level filter system specifically designed for the AMBER experiment at CERN. The novelty of our approach lies in its high efficiency, which eliminates the need for a dedicated on-site computer farm. Instead, it makes use of existing shared resources housed in the CERN data center. The proposed system efficiently handles the data generated by the medium-sized experiment and performs numerous parallel filtering tasks in an online fashion. All system components operate within a shared, fully virtualized environment, including databases, storage, and processing units. This flexible environment scales effectively, allowing adjustments to allocated resources based on agreements with service managers. We present the architectural design and the implementation of such a system. To demonstrate its capabilities, we have conducted various measurements assessing its performance, latencies, and stability under maximum (expected) loads. These results demonstrate the resilience and reliability of the filtering system while optimizing overall costs to a minimum.
Speaker: Martin Zemko (Czech Technical University in Prague (CZ)) -
3
The DUNE DAQ Application Framework
The Deep Underground Neutrino Experiment (DUNE) is a next-generation neutrino experiment that will probe the properties of these elusive particles with unparalleled precision. It will also act as an observatory for neutrino bursts caused by nearby supernovae, in the event that one occurs while the experiment is in operation. Given these goals, the DUNE trigger and DAQ system must be able to maintain extremely high uptime and provide a path for full readout of the detectors for very long times (up to 100s). To achieve these ends, we have designed the DUNE DAQ system around a flexible “application framework”, which provides a modular interface for specific tasks while handling the interconnections between them. The application framework collects modules into applications which can then be interacted with as units by the control, configuration and monitoring systems. One of the key features of the framework is its communications abstraction layer, which allows for modules to interact with both internal queues and external network connections with a single transport-agnostic interface. We will report on the architecture and features of the framework.
Speaker: Eric Lewis Flumerfelt (Fermi National Accelerator Lab. (US)) -
4
Software-Assisted Event Builder for Belle II Experiment
In this paper, we present the design of the hybrid
event builder algorithm for the Belle II DAQ. The event builder
is implemented in PCIe40 FPGA boards and reads up to 48
127 MB/s channels per board. The first version of the event
builder impemented the algorithm entirely in the firmware of
the FPGA. But due to limited onboard memories, there are
hard limitations on the operation conditions. The new algorithm
employs independent event processing for each channel in FPGA,
and a highly-optimized read-out software for final event building.
This allowed us to increase the throughput of the system from
600 MB/s to 3 GB/s on a read-out computer with 20 CPU cores.
The system is currently being commissioned and will be used in
the upcoming data taking period starting in December 2023.Speaker: Dmytro Levit (KEK IPNS) -
12:10
Coffee Break
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5
Network-distributed Data Acquisition System for Photoproduction Experiments with LEPS2
This paper presents the development and current status of the new data acquisition (DAQ) system of photoproduction exepriments with the LEPS2 detector at SPring-8. The LEPS2 DAQ system is based on the network-distributed DAQ-middleware framework, which includes gatherers collecting data from detector sub-systems, mergers integrating data
from gatherers, event builder and logger writing data on files in the data acquisition software. The 10K TPC pad signals are fed up to 16 channels FADC boards and transferred through the SpaceWire protocol to DAQ software components. We have successfully commissioned the DAQ system of the LEPS2 detector comprising a time projection chamber (TPC), drift chambers, resistive plate chambers, Pb/scintillator sampling calorimeters, and neutron counters. The LEPS2 DAQ system reads approximately 10K channels from TPC and 5K channels from other detector components at 100-200 Hz trigger rate and 40 MB/s event size.Speaker: Sun Young Ryu -
6
Optimization of the Upgraded Timing Distribution System of the LHCb experiment at CERN
The Timing Distribution System of the LHCb Experiment at CERN employs FPGA firmware cores to ensure synchronicity across all Front-End and Back-End modules of the Detector Readout System. The control signals are centrally generated in an FPGA-based card, the Readout Supervisor (SODIN), which receives the LHC synchronous clock, and packs timing and control signals into data words (TFC data), distributing it downstream with fixed and deterministic latency. The TFC system is divided into two levels of hierarchy. SODIN transmits the TFC data to FPGA-based Control Cards, which recovers the clock and control signals and forwards them to the Readout Cards and the Front-End modules.
While the clock is recovered at the Control and Readout Cards with a fixed phase within a window of 30ps, at the Front-End modules such window is measured to be 4ns, causing a time-alignment shift of up to 4ns after each clock loss. The reason is that the FPGA internal PLL used for generating the reference clock for the transceivers and the external PLL used for jitter-cleaning don’t keep the same input-to-output phase after a loss of lock.
This paper focuses on the components responsible for timing distribution between the Control Cards and the Front-End modules, achieved through individual bidirectional control links implemented using the GBT-FPGA firmware core. Different firmware and clock routing alternatives were studied for such a link, reducing the window from 4ns to the order of tenths of picoseconds. This paper describes such implementations and the results obtained with each of them.Speaker: Mauricio Feo (Technische Universitaet Dortmund (DE)) -
7
The Level-1 Topological Processor for ATLAS Phase-I upgrade and its firmware evolution for use within the Phase-II Global Trigger
The increased instantaneous luminosity of the LHC in Run 3 brings the need for the upgrade of the ATLAS trigger system. The newly commissioned Phase-I L1Topo system, which replaces its Phase-0 predecessor, processes data from the Feature Extractors (FEXes) and the upgraded Muon to Central Trigger Processor Interface (MUCTPI) to perform topological and multiplicity triggers. The L1Topo system consists of three ATCA modules, each hosting two processor FPGAs (Xilinx Ultrascale+ 9P). The L1Topo firmware is composed of a large number of sort/select, decision, and multiplicity algorithms, that are automatically assembled and configured based on the provided trigger menu. For the HL-LHC, the Phase-I L1Topo system will be replaced by a Global Trigger, a time-multiplexed system, which concentrates the data of a full event into a single FPGA. In order to match the new operational environment, the fully synchronous, very low latency (new data arriving every 25 ns), parallel implementation (~2.5m LUTs) of the Phase-I Topological firmware is being adapted to a significantly higher latency budget (new data arriving every 1.2 us) and a substantially tighter resource budget (~100k LUTs). The main challenge is to allow for multiple working points of the utilized resources and latency for each algorithm. A detailed overview of the Phase-I L1Topo hardware and firmware is provided. Preliminary performance results achieved by the Phase-I L1Topo together with a description of the challenges found during the commissioning process are included. Phase-II related firmware adaptations are also discussed.
Speaker: Viacheslav Filimonov (Johannes Gutenberg Universitaet Mainz (DE)) -
8
The primarily design of 30-channel data acquisition system for 1-ton prototype detector of Jinping Neutrino Experiment
The JNE(Jinping Neutrino Experiment) experiment is located in an underground laboratory in Jinping Mountain, China, with the ultimate goal of building a 500 ton detector with 4000 channels for detecting and studying solar neutrinos. This goal poses a huge challenge to electronic design. Therefore, 30-channel data acquisition system will be built for the 1-ton prototype detector to verify the electronic performance. This paper designs and tests 6 data acquisition(DAQ) boards and 1 Trigger &Time (TT) board used in 30-channel system. Each DAQ board has 6-channel 1GSPS 13-bit ADCs with ENOB(Effective Number of bits) greater than 9.5. The QSFP link Open UI on the DAQ front panel is greater than 55%. The maximum skew value of the synchronization clock between DAQ boards is 85.6ps. The test results indicate that the hardware performance meets the requirements for building a data acquisition system. This also provides a foundation for the development of 4000-channel system.
Speaker: Yan Yang Hao (清华大学工程物理系)
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10:00
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Mini-Orals, Orals Presentations
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9
Mini Orals Session I
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10
Assessing NI FPGA-based platform with MXIe interface for use in ITER hard real-time investment protection applications
The ITER Interlock Control System assumes a crucial role in the tokamak operation to protect the machine against failures. Consequently, it must be developed in compliance with the most challenging requirements. The NI CompactRIO technology was chosen by ITER as the FPGA-based platform to develop and implement the investment protection functions, with strict time-constraints. This contribution focuses on the specific requirements for the ITER Advanced Protection System where the disruption mitigation control function requires a sequenced release of hydrogen ice pellets with jitter lower than 1ms.
The cRIO platform used is the NI9159, which provides an MXIe interface (using a PCIe bridge) to interface the Virtex 5 LX110 FPGA with a host computer running a Linux preempt kernel. ITER decided to improve two important requirements: the MXIe interface communication latency by redesigning the ITER NI-RIO Linux device driver; and the ability to time events in the FPGA logic by designing a specific firmware module based on the Precision Time Protocol (ITER TCN). This contribution details the design methodology followed, the firmware and software elements implemented, the performance obtained in latency and time-keeping accuracy of the approach.Speakers: Damien Karkinsky (ITER), Mr Ignacio García Siguero (Universidad Politécnica de Madrid) -
11
Real-Time Instability Tracking with Deep Learning on FPGAs in Magnetic Confinement Fusion Devices
Active feedback control in magnetic confinement fusion devices is desirable to mitigate plasma instabilities and enable robust operation. Optical high-speed cameras provide a powerful, non-invasive diagnostic and can be suitable for these applications. In this study, we process fast camera data, at rates exceeding 100kfps, on in situ Field Programmable Gate Array (FPGA) hardware to track magnetohydrodynamic (MHD) mode evolution and generate control signals in real-time. Our system utilizes a convolutional neural network (CNN) model which predicts the n=1 MHD mode amplitude and phase using camera images with better accuracy than other tested non-deep-learning-based methods. Open source tools such as hls4ml are used to optimize, translate, and synthesize the CNN to a register transfer level description for FPGA deployment. By implementing this model directly within the standard FPGA readout hardware of the high-speed camera frame grabber, our mode tracking system achieves a total trigger-to-output latency of 17.6us and a throughput of up to 120kfps. This study at the High Beta Tokamak-Extended Pulse (HBT-EP) experiment demonstrates an FPGA-based high-speed camera data acquisition and processing system, enabling application in real-time machine-learning-based tokamak diagnostic and control as well as potential high-speed applications in other scientific domains.
Speaker: Ryan Forelli (Lehigh University) -
12
Integration of Hardware Acceleration Techniques in Real-Time Framework using FPGAs devices
This contribution explores the feasibility of using high-level C/C++ like languages to achieve the integration of specilied FPGAs-based applications with the function blocks of the ITER Real-Time Framework (RTF). RTF enables the development, deployment and execution of instrumentation and control (I&C) applications optimized for real-time performance on ITER CODAC Core System. High Level Synthesis (HLS) and OpenCL are high-level synthesis languages that allow users to implement complex algorithms on FPGA deevices using C/C++ programs. From this perspective, using FPGAs allows to increase the computational power limiting the latencies of a specilied functional block that is run in RTF. The proposal presented notably reduces development time and maintenability compared to the solutions based on Hadware Description Languages, such as VHDL or Verilog.
Speaker: Cesar Gonzalez Brito (Universidad Politécnica de Madrid) -
13
Development of a Fast Timing ASIC for Large-area SiPM Array Readout
The detector of tRopIcal DEep-sea Neutrino Telescope (TRIDENT), hybrid digital optical module (hDOM), employs large-area silicon photomultiplier (SiPM) arrays combined with photomultiplier tubes to boost photon detection efficiency and pointing capability. The experiment requires that the time response of the single photon signal read out by the SiPM array is less than 300 ps (full width at half maximum, FWHM). A fast timing ASIC is designed to read out the fast signal of the SiPM array with a square centimeter area (dozens of S13360-3050CS). Each SiPM in the array can generate a trigger signal. The trigger signals of multiple channels are combined into one channel and output to the off-chip TDC in the LVDS standard. The post-simulations show that the timing jitter is less than 200 ps (FWHM) with the single photo-electron signal input. Compared to the discrete device readout approach, this ASIC has the advantages of higher integration and lower power consumption.
Speaker: Mingxin Wang (Shanghai Jiao Tong University) -
16:05
Coffee Break
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14
Implementation of a Remote Monitoring System for the JUNO experiment
The Jiangmen Underground Neutrino Observatory (JUNO) is an important particle physics experiment. The Detector Control System (DCS) in the experiment needs to monitor a lot of indicators, including environmental temperature, humidity and the operational status of electronics hardware devices. This presentation outlines a remote monitoring system, part of DCS, which is based on Experimental Physics and Industrial Control System (EPICS). The system collects environmental data through a Programmable Logic Controller (PLC), and collects the data of front-end hardware devices through a server. The Input/Output Controller (IOC) development of the front-end hardware devices based on Modbus protocol and other non-standard protocols is realized on the EPICS platform, which will be communicating between the front-end hardware device and the server and will be archiving the data through the PyEPICS interface. The remote monitoring system includes the functions of data acquisition, data archiving, data monitoring and alarming. It can monitor the temperature, humidity in the laboratory and the operating parameters of the front-end hardware devices in real-time. Moreover, it plays an important role in the electronics system coordination and Photo-Mutiplier Tube (PMT) light-off test in JUNO. The application of this system in JUNO verified its effectiveness and stability, and also provided a useful experience for the design of monitoring systems for similar experiments.
Speaker: Shenghui Liu (中国科学院高能物理研究所（IHEP）) -
15
Evaluation of timing and pulse shape analysis method for the measurement of photoneutron energy distribution using commercially available digitizer
Photonuclear reactions induced by high-energy photons play a pivotal role in nuclear physics and radiation transport simulation that is used for medical and industrial applications of high-energy photons. In the transport simulation, not only the photonuclear reaction cross section but also the energy distribution of secondary particles, especially neutrons, is essential because the behavior of neutrons strongly depends on their energies. Experimental studies on the measurement of neutron energy distribution have been carried out for photonuclear reactions for tens of MeV monoenergetic linearly polarized photons.
In this experiment, the emitted neutron energy distribution was obtained by using the electronics circuit and detector for the time-of-flight method and particle identification. The former requires nano-second timing measurement and the latter distinction of mili-Volt order signal difference. Because of the availability of a Ghz sampling digitizer, field programmable gate arrays (FPGA), and fast interface, the procedure can be done using commercially available single-board electronics.
This presentation addresses the above-mentioned data-taking using a 1 GHz sampling rate, 14-bit resolution, FPGA real-time signal processing, 1 MHz throughput digitizer (APV8104 by TechnoAP Co), as well as a comprehensive overview of the motivation, emphasizing the importance of energy spectrum. The data obtained by the digitizer are evaluated from the view of this application. In addition to this, we analyzed raw digitized data that can be obtained from the digitizer for further development to achieve better timing and signal difference analysis in comparison with the simple traditional scheme implemented in the FPGA of the module.Speaker: Dr Kim Tuyet Tran (High Energy Accelerator Research Organization (KEK) Japan) -
16
Design of a fast readout CMOS pixel sensor for the first prototype of CEPC Vertex Detector
CMOS pixel sensors are attractive for the design and construction of the CEPC (Circular Electron Positron Collider) vertex detector due to the low material budget, high spatial resolution, fast readout speed and low power consumption. A series of CMOS pixel sensors were developed for CEPC vertex detector with different study purposes. This study aims to construct a fully functional large-scale CPS for the first CEPC vertex detector prototype. In order to satisfy the high hit rate in the CEPC vertex detector, we adopted a fast in-pixel readout combined with a hit-driven readout architecture in the pixel array, and designed a fast peripheral readout circuit combined with real-time data compression and sharable FIFO tree. The simulation results indicate that the hit rate of 120 M pixels/s can be satisfied. In the chip test, the time walks are about 60 ns to 90 ns under different power consumptions viewing from the statistics of digital output. Finally, 24 chips were installed in the first 6-layer CEPC vertex detector prototype. In the beam test, a spatial resolution of below 5 μm can be achieved and the detection efficiency is about 99%.
Speaker: Xiaomin WEI -
17
Integration of Hyper-Kamiokande Electronics and Test in Super-Kamiokande
Hyper-Kamiokande (HK) is a next generation neutrino experiment planed to start in 2027. The detector will be the largest ever water Cherenkov detector with 260kton water tank and more than 20k photomultiplier tubes (PMTs) on the wall. The detector’s large scale and high performance require various challenges on the electronics and DAQ. The design of the HK electronics has been almost finalized, and final prototypes of the components were delivered in 2023.
The prototypes of the components were interconnected one by one, such as data flow path, clock synchronization path, slow control path and so on. After all, HK electronics were integrated into a system.
After the integration of the components in laboratory, the vertical slice setup of HK electronics was connected to HK Box&Line PMTs in quality checks facility for mass production PMTs. And the requirements of HK electronics were confirmed to be met.
Furthermore, the setup was set in Super-Kamiokande (SK) and connected to SK PMTs and HK PMTs which were installed in the SK tank. That was the first time for HK electronics to take data from water Cherenkov detector. HK PMT and HK electronics were confirmed to work together as a water Cherenkov detector. It’s one of milestones for HK collaboration.Speaker: Yousuke Kataoka (University of Tokyo (JP)) -
18
Scalable KSTAR Real-time Diagnostic Infrastructure Supporting Disruption Prediction and Avoidance
The KSTAR (Korea Superconducting Tokamak Advanced Research) DPA (Disruption Prediction and Avoidance) project led by Steve Sabbagh and Columbia University established a need for increased real-time diagnostic inputs to the KSTAR PCS (plasma control system) to support the real-time evaluation of DECAF (Disruption Event Characterization and Forecasting) algorithms. Over several years, the DPA project installed real-time acquisition of MHD (magnetohydrodynamic), ECE (electron cyclotron emission), and ECEI (ECE imaging) diagnostics, while starting development of a real-time version of vPhi charge exchange Spectroscopy. Each diagnostic shares a common real-time infrastructure that has scaled well between multiple computers and across scientific domains. For example, MHD uses an FPGA, ECE and ECEI use analog digitizers, and vPhi uses a camera system. The various computers communicate over a low latency, high throughput, real-time safe native PCIe link while maintaining compatibility with the existing KSTAR PCS system and its RFM (reflective memory) communication technology. The software framework includes a real-time OS, instrumentation tools, interfaces for archiving and real-time concurrency, and specific I/O device controls. The software also interfaces with PCS itself, with parts of the core PCS running on each real-time system providing entry points for new diagnostic data. This system ran successfully in the 2021 and 2022 campaigns and demonstrated efficient scalability between fundamentally different diagnostic and scientific needs. Each diagnostic, the interconnect, and the underlying software environment will be described with respect to real-time characteristics.
This work was supported by DOE contract No. DEAC0209CH11466 and grant DE-SC0020415.
Speaker: Keith Erickson
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9
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18:15
Welcome reception
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09:00
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Invited Talk, Oral and mini Oral presentations
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19
Invited Talk: Radio isotope production on the Dalat Nuclear Research Reactor and new research reactor project.Speaker: Nguyen Kien Cuong
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20
Jefferson Lab streaming readout system
Streaming readout is becoming a paradigm in data acquisition. Future experiments in HEP (e.g. hi-lumi upgrades at CERN) and NP (e.g. SOLID at JLab and ePIC at BNL) already opted for a modern triggerless DAQ that provides unprecedented possibilities in collecting an unbiased data set, include (quasi) real-time data processing based on sophisticated AI-supported algorithms, and shortening the time between data collection and physics observables extraction. Jefferson Lab, with four experimental halls fully engaged in the 12 GeV scientific program, offers the unique opportunity to test SRO solutions at the intensity frontier shaping tomorrow's experiment DAQ pipelines.
In this contribution, I will report the current efforts at Jefferson Lab to deploy an SRO system based on micro-services as well as the results of on-beam tests performed to validate the different components and profile performance of the whole system. Plans to use the current CLAS12 experiment as a test bed of JLab SRO DAQ will also be discussed.Speaker: Marco Battaglieri (INFN-GE) -
21
Implementations of streaming DAQ on actual detector systems
Detector systems in modern nuclear and particle experiments must handle a large number of channels and high data rates.
In addition, the requirements for triggering systems have become more complex and faster decision making is required.
Streaming readout and software-based triggering on distributed computers is a natural solution to these problems due to recent technological advances.
Therefore, we develop a widely usable streaming data acquisition system based on FairMQ and the Redis key-value database.
The DAQ system is relatively simple and can be developed and operated by a few people.
It works with the cooperation of a large number of simple functional processes, and their connections are automatically set up based on port name, service name and their connection information in a database.
The DAQ system was applied to actual detector systems, the RCNP Grand RAIDEN spectrometer and the J-PARC E50 detector system beam test with streaming readout and online software trigger.
The two detector systems, consisting of plastic scintillation counters and drift chambers, were read out by an FPGA-based streaming readout TDC and distributed synchronized clock, where the charge information was obtained from the time-over-threshold.
The streaming readout DAQ worked well, including online triggering, on 12-core server PCs.
And also the software part of the DAQ was tried to read out a triggered DAQ system for a cylindrical drift chamber for the J-PARC COMET experiment.
This application worked well with sufficient performance.
This report explains the streaming capable DAQ system and its actual application, mainly from the software side.Speaker: Youichi Igarashi (KEK) -
22
First application of a streaming-readout data-acquisition system, products of SPADI Alliance, to physics experiments at RCNP towards the standardization
A new streaming-readout data acquisition system (S-DAQ) developed by SPADI Alliance has been employed in the physics experiment for the first time, which has been performed using the Grand Raiden magnetic spectrograph at RCNP. Signals from two vertical drift chambers and three plastic scintillators are processed by using amplifier-shaper-discriminator boards and charge-to-time converter, respectively. The timing signal with width corresponding to the charge information is digitized by hi- and low-resolution TDCs equipped in AMANEQ streaming-readout front-end electronics. Nine AMANEQ boards are clock-synchronized using MIKUMARI protocol. The data is continuously readout and processed by a data acquisition software NestDAQ. The data is analyzed by using a root-based software ARTEMIS. The total data rate achieved 0.2 Gbps and corresponding event rate achieved 100 kcps, which is ten times faster than the existing trigger-based VME based data acquisition system. Such a high throughput readout enabled us to perform the physics experiments to measure rare events with S/N < 0.1%. The achieved data rate is too high to write all the data and the online filtering process to reduce unphysical or unusable data. The development of this filter is ongoing by using the data simultaneously accumulated during the physics run. In this paper, the setup of the first application of S-DAQ and the performance optimization during the run will be reported and the possible filtering process and its performance will be discussed.
Speaker: Shinsuke Ota (RCNP, Osaka University) -
10:40
Coffee Break
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23
Mini Orals Session II
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19
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Poster A
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24
A 1D CNN Algorithm for Low Background β Detection with Time Projection Chamber
This study investigates the application of machine learning in the realm of low background β detection and identification. Leveraging Convolutional Neural Network (CNN) algorithms, the research involves complex waveform data generated by the Charge-Sensitive-Amplification (CSA) electronic system within the TPC detector. The experimental results demonstrate outstanding performance in actual measurement datasets for low background β detection, effectively filtering out β background events. This investigation not only presents a viable approach for particle identification in TPC detectors through machine learning but also emphasizes the significance and potential applications of machine learning methods in contrast to traditional background rejection techniques within particle physics research.
Speaker: Zengxuan Huang -
25
A 20 Gbps PAM4 Receiver ASIC in 55 nm for Detector Front-end Readout
With the continuous development in the high-speed optical data transmission systems for the detector front-end readout application, the PAM4 technique starts to emerge with its advantages of lower analog bandwidth requirement and less channel numbers.This paper presents the design and test results of a full-function 20Gbps PAM4 receiver ASIC fabricated in 55nm CMOS technology for detector front-end readout of high energy physics experiments.This 20Gbps PAM4 receiver ASIC mainly consists of an equalizer, a voltage shifter, 3 hysteresis-amplifiers, a decoder and a 10Gbps CDR.The voltage shifter shifts the common mode level of one PAM4 signal output from equalizer to obtain three PAM4 signals with different common mode levels for subsequent circuit decision and decoding.The 3 PAM4 signals output by the voltage shifter will be further amplified by 3 hysteresis-amplifiers respectively. Three MSDFFs (Master Slave DFFs) after the 3 hysteresis-amplifiers will resample the three signals and the sampling clock will be provided by the 10GHz clock recovered by CDR. The sampled signals will be sent to decoder for processing to obtain two NRZ signals. The PAM4 Receiver ASIC has been designed in 55nm CMOS technology with the chip area of 1.4mm×2mm.The full-chip post-layout simulation results show that two 10Gbps/ch NRZ data (MSB/LSB) can be correctly received and decoded from the 20Gbps PAM4 signal with a simulated ISI jitter of 1.3ps and 2.6ps, respectively. This PAM4 receiver ASIC has been taped out and the chip test will be conducted in one month, the results will be presented and analyzed in the full paper.
Speakers: Qiangjun Chen, Prof. Di Guo (Central China Normal University) -
26
A 3D track reconstruction algorithm for the pre-research of STCF MDC L1 trigger
The proposed STCF (Super Tau Charm Facility) is an electron-positron collider with high luminosity. Considering the high radiation and counting-rate environment and the pure physics event rate up to 400kHz, it becomes crucial for the Level 1 trigger system to suppress the background to an acceptable rate. Now we present the 3D track reconstruction algorithm for the pre-research of STCF MDC L1 trigger, which can reject tracks outside of the interaction region and present 3D track information to the Global Trigger Logic of L1 trigger for further analysis with other subdetectors. Using the hit information of the Main Drift Chamber (MDC) and transverse momentum and azimuthal angle from previous work of 2D reconstruction, the z (longitudinal) position of the track vertex and the polar angle (θ) concerning the z-axis are reconstructed based on a neural network approach. The phase space of transverse momentum (pt > 0.2GeV) is divided into eight intervals to achieve a high resolution. The neural network for each interval has an identical structure but different parameters. The resolution of z-vertex reconstruction of a single track (z \in [-50, 50]cm) ranges from 0.8cm to 2.7cm, supposed to reject beam background tracks with a ±3σ interval. Two approaches will be taken to implement the neural network. One is using Verilog Hardware Description Language, which we have related work. The other approach produces an IP whose latency is less than 90ns with HLS and the Python package hls4ml. The resource utilization is still under optimization.
Speaker: Yidi Hao (University of Science and Technology of China) -
27
A Full Digital Servo for Ultra-Stable Laser Frequency Stabilization
The paper presents a fully digital servo designed for ultra-stability laser. To minimize laser frequency instability, the system requires high bandwidth and precision, low input and output noise, and minimal temperature drift. The laser system utilizes the Pound-Drever-Hall (PDH) method, employing an ultra-stable cavity to generate an error signal for servo input. This error signal is digitized by a high-speed and precision ADC and transmitted to Field Programmable Gate Arrays (FPGA). The FPGA accurately processes the signal at high-speed using IIR filters and a PID algorithm. The computed results are then converted into an analog signal through a high-speed DAC. The DAC output is then sent back to the laser, eventually stabilizing the laser. Due to the calculation process, the digital servo is inherently slower than its analog counterpart, often constraining the system's feedback bandwidth.
Nevertheless, a digital servo can still attain the same frequency stability goal with sufficiently low latency. A fully digitalized, high-performance servo can be applied in diverse experimental scenarios by making some feedback design modifications. Besides, High-order filters and automatic relocking features are more achievable in digital servo. This design is anticipated to possess sufficiently low latency to overcome the digital servo's bandwidth limitations while retaining maximum flexibility.
Speaker: Zhengtao Liu -
28
A new methodology of clock phase adjustment in a large-scale clock distribution system for HL-LHC ATLAS TGC front-end electronics
Accurate clock distribution to front-end electronics is crucial in optimizing physics performance in collider experiments, especially for triggering applications. In the ATLAS detector, the Thin Gap Chamber (TGC) system performs fast online muon reconstruction using a coincidence algorithm as part of the first hardware-based triggering stage. Preparing for the High Luminosity LHC (HL-LHC), an upgrade to the entire TGC trigger and readout electronics system for the ATLAS experiment is planned (Phase-2 upgrade). During the initial stages of trigger and readout, electronics conduct precise assignment of individual rising edges of binary hits from the TGC chambers to specific bunch crossings. Here, clock phase adjustment plays a vital role in maximizing correct identification performance. This process involves 1,434 frontend electronics, with clock signals distributed via 1,434 optical fibers and reconstructed individually in the Phase-2 TGC system. For effective bunch-crossing identification in TGC trigger electronics, clock tuning well below O(1) ns is necessary. We've developed a methodology for measuring the clock phase for individual reconstructed signals across the entire system comprising 1,434 frontend modules and aligning the phase remotely and automatically in situ. Two custom VME modules were designed for this purpose, thoroughly tested, and proven to be fully functional. This presentation presents a methodology developed to ensure low-skew clock signal distribution, focusing on efforts to maintain aligned clock signals across the large-scale electronics system. A measurement-driven estimation of the expected size of skew to be absorbed and the expected uncertainties on the alignment will also be discussed.
Speaker: Mr Ren Nagasaka (University of Tokyo (JP)) -
29
A Plugin-Based Software Framework for Data Acquisition and Processing
In response to the diverse requirements for data acquisition and online data processing in scenarios such as high-energy physics detector research and pre-research experiments, this talk proposes a highly scalable data acquisition and online data processing software framework based on the modular design concept. The framework represents the readout and data processing processes as basic data processing units. It could simplify the creation of processing unit classes based on a C++ designed dependency injection pattern. Within the framework, processing units can be freely assembled to form data processing workflows through configuration files. Additionally, users can develop electronics interaction plugins to meet various electronics configuration and readout requirements, and generate data streams that fulfill the requirements of different experiments through configuration files. This framework presents an easier solution for data acquisition and online data processing in high-energy physics experiments.
Speaker: Shaoshuai Fan (ihep) -
30
AN ASSESSMENT OF EXTERNAL DOSE FROM NATURAL RADIOACTIVITY IN BUILDING MATERIALS BY USING SIMULATION MONTE CARLO
Abstract:
It is important to determine the external dose due to the radiation emitted from building materials because individuals spend most of their time in their residence or office. In general, the radioactive isotopes 226Ra, 232Th, and 40K exist naturally in soil, rocks, and sand. When these materials are used in construction, the gamma radiation of natural radionuclides emitted from walls, floors, and ceilings could cause radiation exposure to humans. In this study, a room model with dimensions of 4m × 5m × 2.8 m and a wall thickness of 20 cm was built using the MCNP6 code. The simulation model was used to assess the external dose from the natural radioactivity of building materials in the human body. The absorbed dose from phantom water was calculated using a Monte Carlo simulation. Besides, a similar room model was performed with the RESRAD-BUILD code to compare the results obtained from the MCNP6 software.
Key words: external dose, absorbed dose, Monte Carlo, MCNP6, RESRAD-BUILDSpeaker: Tran Thi Bao Ngoc -
31
An FPGA-Based High Precision Pulse Width Measurement Time-to-Digital Converter with Time Division Multiplexing Encoder
High-precision Time-to-Digital Converters (TDCs) play a pivotal role in contemporary high-energy physics experiments where the measurement of time-over-threshold (TOT) of nuclear pulses is essential.
This paper introduces an innovative FPGA-based TDC capable of outputting timestamps for both rising and falling edges. The hit signal's edges initiate two identical segments of clock-like signals, respectively encompassing timing information from the rising and falling edges, which then propagate along the TDL. Employing the proposed Time Division Multiplexing (TDM) multi-edge encoder in a pipeline configuration allows for the meticulous extraction of timestamps from the TDLs status.
In this study, a 4-edge wave union TDC is implemented, demonstrating proficiency in discerning timings for both rising and falling edges. The corresponding root mean square (RMS) precisions for time intervals ranging from 0 to 10 ns are consistently calculated at approximately 5.0 ps. The TDC measurement dead time corresponds to two system clock cycles, and the minimum discernible pulse width is constrained by the upper limit of the FPGA transmitting port. By leveraging the resource-efficient attribute, a 64-channel TDC, possessing equivalent characteristics and an RMS resolution below 10 ps, is instantiated within a single Kintex-7 device. The FPGA logic resource utilization ranges from 30% to 40%, substantiating the proposed TDC structure as notably compact and highly advantageous for the integration of multiple channels in high-energy physics experiments.Speaker: Wenhao Duan (State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China) -
32
An Improved Algorithm for Q-scale Analysis in Jitter Decomposition
High-speed transceivers are the essential component of data acquisition systems for high energy physics (HEP). When the data rate increases to several gigatransfers per second (GT/s), jitter becomes one of the bottlenecks limiting the data transfer rate. Total jitter can be modeled as a superposition of an unbounded random component that follows a Gaussian distribution and a bounded deterministic component. In this work, an improved algorithm is proposed for Q-scale analysis by estimating a parameter values of DJ and selecting a dynamic fitting interval. The validation results indicate that the error between the measured values and theoretical values is less than 5%, which is better than traditional algorithms. At the same time, the algorithm has better measurement stability and higher data utilization.
Speaker: Mr Xiangshi Zhong (University of Science and Technology of China) -
33
An investigation of a stilbene organic scintillator for fast neutron detection at Acculinna-2
For the demand of studying a set of resonant states of several neutron-rich nuclei (6H, 7H, 7He, 10Li, ...) lately at ACCULINNA-2 [1], a neutron spectrometer based on stilbene crystals coupling with 3” ET-Enterprise 9822B photomultipliers [2] has been crucially developed and routinely employed in our work. This is to tag principally the reaction channels and practically explore the nuclear structure of light isotopes beyond the limit of β-stability. Nonetheless, the detailed characteristics and properties of stilbene scintillator have not been completely studied and well-understood owing to its intricate response by light output anisotropy with reference to the crystalline structure itself. In this work, we aim at determining the light output responses for electrons and charged ions, having the same initial energy but generating different behaviors when they stop in an organic scintillator. In accordance with the detector performance, energy dependence of time resolution and neutron-gamma discrimination (NGD) of stilbene will be evaluated at different ranges of energy. Also the neutron detection efficiency of stilbene employing monoenergetic fast neutron beam, originated by a continuous neutron flux generator ING-27 [3] in the Frank Laboratory of Neutron Physics, will be investigated as well.
Speaker: Ms Anh Mai (Vietnam National University, University of Science, Flerov Laboratory of Nuclear Reactions, JINR) -
34
Custom 14-Bit, 500MHz ADC/Data Processing Module for the KOTO Experiment at J-Parc
We present a new ADC/Data Processing Module, designed for Step 2 of the KOTO Experiment at J-Parc, Japan. Occupying 18 VME Crates, the current KOTO Step 1 readout system includes three distinctive blocks: the CsI calorimeter readout with 2,600 channels using custom 16-Channel, 14-Bit, 125MHz modules; the veto detector readout with 500 channels and the same type of ADC modules; and the beam hole veto detector readout with 100 channels and custom 4-Channel, 12-Bit, 500MHz ADC modules. Our new 16-Channel, 14-Bit, 500MHz ADC/Data Processing Module with the same 6U VME64 form factor and power requirements as the above mentioned 14-Bit, 125MHz modules, is designed for replacement. A powerful Intel Arria V FPGA is used for real-time triggering with clustering and total energy calculations, data pipelining and data packing. Two QSFP+ optical links will allow for data transfer rates up to 40Gbps per QSFP+ transceiver. Board configuration can be done either via a front panel SFP link or Ethernet port, while an auxiliary RJ45 connector with 4 LVDS lines can be used for system clock synchronization and triggering. The VME64 backplane provides an alternative path for configuration and low-rate data readout, but it is mostly used for initial testing and debugging. The module design will be described, and preliminary test results will be reported.
Speaker: Mircea Bogdan (The University of Chicago) -
35
Data acquisition system of beam loss diagnostics for SKIF synchrotron light source
Data acquisition system of beam loss monitors (BLM) was developed for Siberian ring source of photons (SKIF) which is under construction in Novosibirsk, Russia. The BLM consist of Cherenkov beam loss monitors (CBLM) and scintillator-based beam loss monitors (SBLM), which should ensure the stability of the SKIF operation. Recording system for CBLM is based on two-channel measuring modules operating with 10-bit amplitude resolution, sampling rates up to 5 GHz, with repetition rates up to 10 kHz. These modules based on DRS4 chip (Swiss Institute PSI), working scale-time conversion technology (SCA - switch capacitor array). Four-channel measuring modules are used to record signals from SBLM. They were developed based on the oscillographic data recording method. Each channel of the measuring module provides data recording with a sampling rate of 250 MHz and an amplitude resolution of 14 bits. The CBLM and SBLM measuring modules are combined into the general data acquisition system by cable synchronization lines, linking the data acquisition cycles to external events.
Speaker: Ekaterina Puryga (Budker Institute of Nuclear Physics SB RAS) -
36
Dependence of Detection Efficiency and Neutron/Gamma Discrimination Ability on the Volumetric parameters of EJ-301 Liquid Scintillation Detector
In this work, we investigate the relationship between the volumetric parameters of the cylindrical EJ-301 liquid scintillation detector and its detection efficiency and neutron/gamma discrimination capability. Eight detector configurations corresponding to cylindrical EJ-301 detectors of different length and diameter values connected to a photomultiplier tube have been modeled. Signals corresponding to these models, which were obtained using the Geant4 simulation program, have been analyzed using a neutron/gamma pulse shape discrimination method, i.e., the zero crossing one. The results indicate that the detector’s diameter has an important impact on its neutron detection efficiency, whereas its neutron/gamma discrimination ability strongly depends on its length-to-diameter ratio.
Keywords: neutron/gamma discrimination, EJ-310 scintillator detector, ZC method, Geant 4 simulation.Speaker: Mr Hieu Phan Bao Quoc (Dalat Nuclear Research Institute) -
37
Design and Characterization Challenges of an Attoampere-Sensitive ASIC-Based Ultra-Low Current System for Real-Time Radiation Monitoring
The time budget for a radiation monitoring system to accurately determine the input dose rate could vary from microseconds to minutes, depending on the operational scenario. For personal protection, the typical requirement is often in the range of milliseconds. Consequently, such systems require a fast analog front end capable of transforming the continuous output of a radiation sensor into discrete quantities. A matching digital system is then needed to convert these quantities into interpretable metrics, such as dose rates. The output of radiation sensors typically manifests as a current, which could range from femtoamperes to microamperes or even milliamperes, depending on the type of sensor and environmental conditions. Hence, the most challenging subsystem in the design of such a radiation monitoring system is the analog front end. The radiation protection group at CERN has developed an Application-Specific Integrated Circuit (ASIC)-based front end to digitize the currents generated by an ionization chamber. The ASIC has demonstrated a sensitivity of 200 aA under controlled environments. Various aspects were considered during the design process, from tuning the correct simulator settings to selecting the optimum architecture and transistor variants, as well as effectively shielding the sensitive components. This paper summarizes the challenges faced and the methodologies adopted in successfully designing such a front end. The setup used for characterizing such a system is also described in detail.
Speaker: Dr Sarath Kundumattathil Mohanan (CERN) -
38
Design and development of JUNO DAQ Data Flow Software
The Jiangmen Underground Neutrino Observatory (JUNO) is a neutrino experiment under construction with a broad physics program in southern China. The primary physics goal of JUNO is to measure the order of neutrino mass. The front-end electronics of JUNO will generate approximately 40GB/s of raw data, including data in various formats from multiple detectors. A large distributed data acquisition (DAQ) system needs to be developed and designed.
The JUNO DAQ system is mainly divided into data flow software and online software. The data flow software is responsible for the readout, online processing, and storage of raw data, while the online software provides services such as software configuration and operational control.
This presentation will introduce the design architecture of the JUNO DAQ data flow software, and will discuss the recent progress in software development by incorporating relevant test results.
Keywords: JUNO DAQ dataflowSpeaker: Chao Chen (IHEP) -
39
Development of FPGA-Based Nuclear Electronics using NI MyRIO Hardware for Small-Scale Radiation Detector Systems
Coincidence electronics and pulse height analyzers stand as pivotal techniques in radiation detection
systems. The development of FPGA-based nuclear electronics has garnered attention due to their
programmability, simplicity, testability, compact size, and low power consumption. This technology is
increasingly favored worldwide for nuclear electronic systems over traditional analog counterparts. This
study presents advancements in coincidence electronics and a Pulse Height Analyzer (PHA) utilizing
commercial FPGA-based (Field-Programmable Gate Array) hardware for radiation scintillation
detectors. The hardware, based on a cost-effective NI myRIO device, integrates a Field-Programmable
Gate Array (FPGA), ARM Cortex-A9 processor, analog input (AI), digital input and output (DIO), and
USB/wireless connectivity with a host computer. LabVIEW codes, developed on the LabVIEWTM
platform, are implemented in NI myRIO hardware for seamless integration and computer interface. The
FPGA-based coincidence electronics performance is assessed through an experimental setup for the
gamma-gamma angular distribution of a Na-22 radioisotope source. Similarly, the FPGA-based PHA
undergoes testing with a NaI(Tl) detector, with a subsequent comparison of energy resolution against a
commercial EASY-MCA 2K from AMETEK Inc.Speakers: Hoang Nguyen Quoc (University of Science - Vietnam National University-Hochiminh City), Hoang Pham Viet (University of Science - Vietnam National University-Hochiminh City), Nguyen Tri Toan Phuc (University of Science - Vietnam National University-Hochiminh City), Phan Lê Hoàng Sang, Phong Nguyen Tan (University of Science - Vietnam National University-Hochiminh City), Trang Hoang (University of Science, Ho Chi Minh City, Vietnam), Trương Thị Hồng Loan (University of Science, VNUHCM, Ho Chi Minh City, Vietnam), Tu Nguyen Hoang (University of Science - Vietnam National University-Hochiminh City), Dr Vo Hong Hai (University of Science, Vietnam National University-Ho Chi Minh City) -
40
Development of the Low Noise Front-end Electronics for Pulse Voltage Stability Measurement
To meet the measurement requirements for the pulse-to-pulse stability of high-voltage output pulses from solid-state pulse modulators, this paper designs a low-noise front-end electronics “SAFee”, which can provide a DC bias of -10 V to 10 V. The offset of the divided voltage pulse is adjusted to near 0 V and then measured with an oscilloscope at a resolution of 1 mV/div, thereby achieving a stability measurement of 50 ppm for voltage pulses up to 10 V. The core part of SAFee is a discrete three-op amp instrumentation amplifier. Its CMRR, output noise and other key parameters have been calculated in detail, and the optimal amplifier LT6018 and precision matching resistor network LT5401 form ADI has been selected. The DC bias circuit is generated by the precision reference voltage LTC6655, 20-bit DAC AD5791 and ultra-precision operational amplifier AD8676. The system is controlled by a module based on Xilinx ZYNQ7010. The test results show that the output noise of SAFee is 150.34±1.13 μV RMS, which can meet the measurement requirements of solid-state pulse modulators with a stability of 50 ppm. In addition, the output voltage and DAC code are scaled, and the goodness of fit R2 can reach more than 0.999999998.
Speaker: Mr Lin Jiang (Tsinghua University) -
41
Digital oscilloscope-based acquisition for fast and dynamic sampling of photodetector signals
A digital oscilloscope can trigger with a mV threshold, digitalize analog signals with 500Mhz sampling in a dynamic timing window, and acquire several channels in a fraction of a second. These characteristics provide oscilloscope a distinct advantage when working with small or medium-sized setups that require photosensor signals to be acquired lightning fast. We created a system to study cosmic muon decays using SiPM and plastic scintillators, as well as another using optical fibers and PMT to monitor proton beam loss at the J-PARC neutrino beamline. We will discuss our experiences with these developments.
Speaker: Son Cao (IFIRSE/KEK) -
42
Enhancements and Deployment of the TDAQ System for the Mu2e Experiment
The Real Time Processing Systems Division at Fermilab has deployed new features to the Off-The-Shelf Data Acquisition framework (otsdaq) for the Mu2e experiment. The Mu2e experiment will search for the coherent neutrino-less conversion of a muon into an electron in the field of an aluminum nucleus with a sensitivity improvement of 10,000 times over existing limits. Such a charged lepton flavor-violating reaction probes new physics at a scale unavailable at present or planned high-energy colliders. The Mu2e Trigger and Data Acquisition (TDAQ) system uses otsdaq as its online Data Acquisition System (DAQ) framework. otsdaq integrates the artdaq and art frameworks for event transfer, filtering, and processing. otsdaq is a web-based DAQ software suite focusing on flexibility and scalability and provides a multi-user interface accessible through a web browser. artdaq handles the entire data stream, which is read over the peripheral component interconnect express (PCIe) bus to a software filter algorithm that selects events combined with the data flux coming from a cosmic-ray veto (CRV) system. Detector front-ends are configured through the PCIe bus by customized otsdaq plugins. The otsdaq slow controls infrastructure has been further developed using the experimental physics and industrial control system (EPICS) open-source platform for monitoring, controlling, alarming, and archiving. The detector control system (DCS) for Mu2e has been integrated into otsdaq. The production TDAQ and DCS system has been deployed at the experimental hall and is being debugged and optimized for experiment operations. We report on the feature enhancements and deployment of otsdaq for Mu2e.
Speaker: Javier Campos -
43
Enhancing Neutron/Gamma Discrimination in the Low-Energy Region for EJ-276 Plastic Scintillation Detector Using Machine Learning
Pulse Shape Discrimination (PSD) techniques, particularly the widely employed charge integration ratio method (Qratio), have conventionally proven effective in distinguishing fast neutrons from gamma rays in organic scintillation detectors. However, the utility of Qratio diminishes in the low-energy region (below 100keVee) due to overlapping signatures, leading to a suboptimal Figure of Merit (FOM). In this study, we employ machine learning techniques to enhance neutron/gamma discrimination and compare the results with the traditional charge integration ratio in the low-energy region threshold. Our investigation centers on the EJ-276 plastic scintillator, a commercial product of ELJEN technology acclaimed for its adept separation of gamma and fast neutron signals based on timing characteristics. Experimental data were acquired using Cf-252 and Co-60 radioisotope sources. A comprehensive comparative analysis between the traditional Qratio method and machine learning algorithms is conducted across varying energy thresholds (50keVee to 2000keVee). The primary objective is to rigorously evaluate and enhance neutron/gamma discrimination capabilities in the critical low-energy region.
Speaker: Dr Vo Hong Hai (University of Science, Vietnam National University-Ho Chi Minh City) -
44
ePIC Synchronization and Timing Distribution
ePIC is the first general purpose detector at the EIC (Electron Ion Collider) accelerator complex at BNL.
The data acquisition synchronization among the on-line computers and various detector sub-systems is described. The system includes a Global Timing Unit (GTU), hundreds of Data Aggragation Modules (DAM), and thousands of ReadOut units (RDO), (and countless cables, copper and fiber). The data acquisition deadtime should be minimal, and the jitter of distributed clock should be less than 5ps (relative to the beam).
The GTU interfaces with the collider for the beam synchronous clock and the beam orbital structure, with the run-control for data acquisition, and with DAM boards. The DAM fans out the GTU signals (runcontrol, clock), configures the RDO/FrontEnd Electrocnics including ASICs), passes on the DAQ status. The RDO receives/recovers the beam synchronous clock and distributes to the frontend (ASICs), configures the frontends, and collects data/status and sends to the DAM.
Some conceptual tests were performed and some results are presented. More tests will be performed on the (pre)prototype boards.
Speaker: Jianhui Gu -
45
Evaluation of kinetics parameters of the Dalat nuclear research reactor with LEU fuel
The Dalat Nuclear Research Reactor (DNRR) is the unique pool-type research reactor in Vietnam with the power output of 500 kW. The reactor core was upgraded from a 250 kW TRIGA Mark II research reactor. The DNRR is currently operating with low uranium-enriched (LEU) VVR-M2 fuel type. Kinetics parameters of the reactor core are important parameters to assess the safety operation of the nuclear reactor. In the present work, evaluation of the kinetics parameters, including delayed neutron fraction and prompt neutron lifetime, of the DNRR core loaded with 92 LEU fuel bundles has been conducted using the MCNP 6.2 code and the ENDF/B-VIII.0 nuclear data library. The results show that the delayed neutron fraction at the beginning of cycle is 0.75±0.03 and the prompt neutron lifetime (lp) is 92.31±2.64 (ms). Effect of new nuclear data library (JENDL-5) and the uncertainty of the nuclear data on the calculation results are also being evaluated and presented.
Speakers: Duc Tu Dau, Hoai Nam Tran -
46
Faraday Cup Development for Beam Monitoring in nA Scale and Its Application in the Cross section Measurement of p+12C Scatterings with Ep=1-3.2 MeV
A Faraday cup (FC) suitable for nA intensive beam has been developed to serve nuclear reaction study using the pelletron at the University of Science, Vietnam National University (HUS). Firstly, the FC operation was tested with proton beam of 1-3.2 MeV energies. The diversion of the scattered beam was checked with and without a natural boron target of 0.2 μm thickness on 1.95 μm aluminium substrate. By varying the value, the optimal repeller voltage was found at -350 V which suppressed the secondary electrons from flying out of the cup to ensure the precision of the measuring current. The obtained results were in agreement with the CST simulation’s. Afterwards, the FC was used in the experiment to measure the cross sections of p+12C scattering with Ep=1-3.2 MeV at the angles of 50, 106, 120, 130 and 160 degrees. Except the data at the angle of 50 degrees is new the data at other angles are compared and in good agreement with the published ones.
Speaker: Xuan Chung Le (Institute for Nuclear Science and Technology) -
47
Fault Detection and Diagnosis Software for LHAASO
The Large High Altitude Air Shower Observatory (LHAASO) is designed to observe physical phenomena such as cosmic rays, the occurrence of which is unpredictable and therefore requires uninterrupted operation of the experiment system. However, failures are almost inevitable, and in the event of a system failure, the cause of the failure needs to be quickly analysed and repaired. The Fault Detection and Diagnosis software (FDD) was designed to quickly detect and analyse system faults. The software collects real-time operational status information from various components of the experimental system, including detectors, electronics, and data acquisition software. FDD can quickly analyse the cause of faults when they occur, providing timely information to the experimental maintenance personnel. In addition, historical data for a specified time period can be analysed and data reports generated as required. The design requirements of FDD include high throughput, real-time, expandability and reliability. To meet these requirements, the software adopts a distributed architecture, deploying data collection, processing, storage and presentation functions on different nodes. The software consists of the following components: information collection module, automated operation module, fault analysis module, interaction module, and database. The software analyses the collected parameter data through batch processing and gives the cause of failure using automation. The technical validation and prototype implementation of the system has been completed and applied in LHAASO. FDD can quickly and accurately diagnose operational faults, provide effective solutions for experiment operators.
Speaker: Mr Hangchang Zhang (Institution of High Energy Physics, Chinese Academy of Sciences) -
48
Hi'Beam-SEE: a real-time hgih-resolution Single Event Effects locating device for heavy ion facilities
Integrated Circuits(ICs) are widely used in satellites and aircraft. High energetic particles in the environment such as protons, electrons, and heavy ions will hit these devices causing Single Event Effect(SEE). The probability of the occurrence of SEE and the single event sensitive map of the devices are very concerned by researchers. To improve the efficiency and accuracy of SEE studies, a micrometer-scale positioning device for testing SEE in integrated circuits, named Hi’Beam-SEE, has been developed. The device can be used at the Heavy Ion Research Facility in Lanzhou (HIRFL) and the High-Intensity Heavy-ion Accelerator Facility (HIAF), which can accurately give the distribution of SEE sensitive map of the ICs. The Hi’Beam-SEE system consists of three main components: the heavy ion positioning system is responsible for locating the trajectory of each particle in the beam, the single events detection system is responsible for detecting single event effects that occurred in the device under test, and the GPU-based online data processing is responsible for beam reconstructing and locating the final sensitive map. The prototype of Hi’beam-SEE has been designed. The laser and beam test of the heavy ion positioning system has been carried out, and an excellent spatial resolution has been achieved. A single events detection system has been designed. Data processing algorithms enable detection rates of 110+ fps when processing a single image containing 25+ laser or heavy-ion trajectories.
Speakers: Dr Jianwei Liao (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Chengxin Zhao (Institute of Modern Physics, CAS) -
49
Identifying Regions of Interest in the ATLAS Calorimeter with Deep Convolutional Neural Networks
Clustering of calorimetric signals in the ATLAS detector has typically been performed using the topocluster algorithm, following cell signal-significance patterns. In this work we present a machine learning alternative to topoclustering. Using current topological cell clusters as indicators of physical significance we use a convolutional neural network (CNN) to identify regions of interest in the calorimeter. We introduce a novel data pre-processing pipeline transforming the ATLAS calorimeter into a two-dimensional representation in η,φ; building upon previous treatments of jets as images in particle physics. The performance of the object detection architecture, which targets real-time applications, is evaluated on a set of simulated particle interactions in the ATLAS detector.
Speaker: Leon Bozianu (Universite de Geneve (CH)) -
50
Implementation of a double trigger condition based on Charge Comparison and TOF measurement in an FPGA for the NEDA detector array.
The NEutron Detector Array (NEDA) is designed to improve the sensitivity of gamma-ray spectrometers by enabling the selection of reaction channels by counting evaporated neutrons. The detector cells react with both neutrons and gamma-rays. A double trigger condition system has been implemented in the detector signal digitisation firmware to enhance neutron acquisition and reduce the number of gamma-rays acquired. In the double trigger condition system, two independent triggers are generated: one is based on Charge Comparison (C.C.) and the other on Time-of-Flight (TOF). These triggers can be combined using OR and AND logic, offering four different trigger modes. The system has been evaluated using data from real experiments. The four trigger modes have been applied to the same data and a subsequent offline analysis has been performed. It has been shown that most detected neutrons are preserved with AND mode, and the total gammas are significantly reduced. On the other hand, the OR trigger mode allows increasing the selection of neutrons, compared to the C.C. trigger mode. In addition, it has been demonstrated that if the OR mode is selected, the C.C. threshold can be raised without losing neutrons.
The double trigger condition in NEDA marks a significant leap in spectrometry capabilities. Offering diverse trigger modes (C.C., TOF, AND, and OR) provides researchers detection options, expanding neutron energy detection ranges and enabling control over counting rates. In nuclear physics research, NEDA with its double trigger system elevates precision in identifying reaction channels and enhances data acquisition capabilities.Speaker: Jose Manuel Deltoro Berrio (Universitat de Valencia) -
51
Implementation of multi-GHz digital shaper for high-rate nuclear spectroscopy
In recent years, nuclear spectroscopy has benefited from advances in the field of high-speed digital signal processing (DSP), enabling improved detector response and reduced dead time. The trapezoidal shaper, has been widely used for pulse processing in nuclear spectroscopy applications. Trapezoidal allows to fine tune the energy resolution and sustainable rate by selecting the shaping time. The filter is typically implemented in FPGA using a recursive architecture. At the state of art, the recursive implementation of the trapezoidal filter allows to operate no more than 250-300 MHz on modern devices. However, with the advent of very fast detectors such as photomultiplier tubes (PMTs), diamond sensors, and fast silicon photomultipliers (SiPMs), the demand for even higher-speed implementations has grown.
In this paper, we present a novel high-speed implementation of the trapezoidal shaping method that can operate at up to 5 GSPS for trapezoidal filters with a maximum length of 1024 samples and at 2.5 GSPS for filters with a maximum length of 8192 samples. This significant improvement in speed was achieved by parallelizing all digital blocks within the FPGA-based digital pulse processing architecture.Speaker: Andrea Abba (Nuclear Instruments SRL) -
52
Implementation of the JUNO DAQ Online Software
The Jiangmen Underground Neutrino Observatory (JUNO) is located about 53 kilometers from the Yangjiang and Taishan Nuclear Power Plants to measure the neutrino mass ordering and neutrino mixing parameters precisely. In order to meet the demand of the JUNO experiment for large data acquisition, the data flow software runs on roughly 100 computing nodes. This poses challenges for the online software to manage and monitor the data flow software. Considering the characteristics of JUNO’s data acquisition (DAQ) system, including massive data and continuous operation for over thirty years, the JUNO DAQ online software has been upgraded to improve high availability. This online software enables unified supervision, configuration management, process management, run control, information sharing, and other services for the DAQ system. It employs a microservice architecture to reduce coupling among modules. It also utilizes a container management mechanism based on Kubernetes to optimize software deployment and failover, providing a longer software lifecycle and reliable support for the experiment. Currently, this new online software has been tested with data flow software to integrate the detector and electronics at the JUNO experiment site.
Speaker: Yinhui Wu (Institute of High Energy Physics, CAS) -
53
Implementation of the Trigger, Timing, and Control Link for Data Acquisition with the Pixie-Net XL
A common problem in larger nuclear physics experiments is the distribution of clocks and triggers between multiple types and instances of detector readout electronics. Measurements of the time difference of multiple, coincident interactions in separate radiation detectors, to sub-nanosecond precision, require the data to be time stamped with high accuracy across the system. In addition, background events may have to be suppressed to limit data acquisition to available bandwidth and storage.
Clocks and triggers are traditionally distributed through dedicated cabling. Techniques such as the IEEE 1588 Precision Time Protocol and its high accuracy profile (White Rabbit) can distribute clocks and time/date through generic Ethernet data connections, but do not easily allow sharing of triggers for data acquisition. In contrast, the Trigger, Timing, and Control Link (TTCL) has been developed as a method to distribute both clock and trigger through generic fiber with a specific data exchange protocol. TTCL has been adopted for several experiments and facilities since 2008 and is supported by a variety of readout electronics designs. The related interface described here is compatible with Digital Gammasphere and GRETA.
Specifically, we implemented TTCL for the Pixie Net XL detector readout electronics. A TTCL interface board de-serializes the incoming TTCL data stream, extracts the embedded clock for digitization and time stamping on the Pixie-Net XL, and decodes triggers for the pulse processing logic. We describe design and testing of the interface board, how TTCL triggers can be used to conditionally record events, and report the time resolution of coincident events.Speaker: Wolfgang Hennig -
54
JUNO High Voltage & Low Voltage Power Control System Upgrade Based on EPICS
The Jiangmen Underground Neutrino Observatory (JUNO) is a multipurpose neutrino experiment designed to determine the neutrino mass ordering and precisely measure the oscillation parameters. In this experiment, there were 17612 large 20-inch photomultipliers (LPMTs) and 25600 small 3-inch PMTs (SPMTs), the Detector Control System (DCS) is responsible for the detection and controlling running status of the detector. Due to the large scale of the experiment, tens of thousands of High Voltage Units (HVU) and thousands of Low Voltage Power (LVP) components need to be controlled by the DCS. Therefore, in order to enhance the performance of the DCS, this paper proposes the RWTS-DA (read-write thread separation and data aggregation) scheme. This scheme can effectively reduce the overhead of thread switching and enables faster data assembly for data analysis. Empirical results show that the RWTS-DA scheme improves the performance and data analysis efficiency of the DCS. Consequently, the RWTS-DA scheme can be widely applied in a variety of multi-device and multi-channel control systems based on Experimental Physics and Industrial Control System (EPICS).
Speaker: 黎晃 lihuang -
55
Low-power large-dynamic range readout ASIC for VLAST silicon strip detector
The main scientific goals of the Very Large Area Gamma-ray Space Telescope (VLAST) include indirect detection of dark matter research based on gamma rays, detection of the MeV line spectrum of late kilonovae to confirm the origin of super-iron elements directly, etc. The VLAST plans to use silicon strip detector (SSD) to build a Silicon Tracker and low Energy gamma-ray Detector(STED) to collect the electron-hole pairs converted from the high-energy gamma photons. STED comprises eight super-layers, including eight CsI detection layers and sixteen large silicon strip detection layers, with 344064 channels. Each detector channel has a large equivalent capacitance of ~100pF. The SiReadout is a 16-channel, ultra low-power, low-noise, large dynamic range readout ASIC for the silicon strip detector of VLAST. Each channel mainly consists of the charge sensitive preamplifier, the polarity selection circuit, the shaper circuit, the peak detect and hold circuit, and the discriminator. The input charge dynamic range of the chip spans from -200 fC to 200 fC, the power consumption is less than 270uW/channel, the equivalent noise charge(ENC) for positive charge input is 508e- at zero F plus 1.3e- per pF, the linearity error below 2%. The performance of SiReadout proves it fulfills the requirements of VLAST.
Speaker: Dr Gang Chen (Institute of Modern Physics, Chinese Academy of Sciences) -
56
Magnitude of (d, p) reactions at low-energy using the Faddeev-Alt-Grassberger-Sandhas equation
The Faddeev-Alt-Grassberger-Sandhas (FAGS) equation is well-known the complete, unique and exact 3-body model to describe the (d, p) reactions. The FAGS model is thus typically used as a benchmark for other 3-body techniques. The FAGS calculations, however, are extremely intricate and time-consuming because they take into account the elastic, inelastic, transfer, and breakup reaction simultaneously. The (d, p) reactions at low energy are a special case that I will describe in this paper by simplifying the FAGS equation and some of preliminary results relating to reaction amplitude.
Speaker: Mr Tùng Nguyễn Hoàng (Department of Nuclear Physics and Nuclear Engineering, Faculty of Physics and Engineering Physics, University of Science, Ho Chi Minh City 700000, Vietnam) -
57
Measuring Performance Under Failures in the LHCb Data Acquisition Network
In this paper, we study two possible approaches to high-performance event building on the data acquisition (DAQ) system of the LHCb experiment. We show, using live experiments, that a synchronized design, that carefully schedules network communications to avoid network congestion, can obtain significantly better performance than a looser approach. However, this comes at the price of fault tolerance: we study the performance degradation of the DAQ system in the presence of various link failures, showing that, in these scenarios, the synchronized approach is not optimal. Finally, we derive some design recommendations to make synchronized designs cope with network failures.
Speaker: Eloise Noelle Stein (Universite de Strasbourg (FR)) -
58
Multi setup for giant dipole resonance studies
One of the main tasks of experimental research in the field of nuclear physics was and still is the task of obtaining information about the structure of the atomic nucleus. Such information can be obtained primarily in nuclear reactions. Among the huge variety of nuclear reactions, an important place is occupied by reactions caused by electromagnetic interactions.
The study of the nature and properties of GDR played a decisive role in the development of modern ideas about the structure and dynamics of the atomic nucleus. To study the features of GDR formation and decay, first of all, accurate and reliable information about the energy dependences of the cross sections (excitation functions) of total photoabsorption reactions and various partial reactions caused by photons is necessary.
This work is focus on application of phoswith detectors for separation of the high-energy γ-ray and «pile-up» γ-rays dedicated for studies of GDR.The details of MULTI spectrometer, and DAQ system will be presented.Speaker: Sergey Stukalov (Flerov Laboratory of Nuclear Reactions, JINR) -
59
Multi-port Remote JTAG over Optical Fibers under Radiation Environment
The JTAG protocol is still the most popular method to program the FPGA where a more intelligent technology is not applicable. These days, FPGA is often used in the environment where radiation level is high and space is limited. The original JTAG protocol is based on four lines of single-ended DC-coupled signals, and it is not designed for a long distance connection under such an environment. We designed a circuit made of a small number of discrete devices to receive a custom encoded JTAG protocol (optjtag) from an AC-coupled connection, which is suitable for an optical fiber transport over a long distance. The circuit requires no programmable devices, and uses only a small area on the remote FPGA board. The optjtag protocol can be easily implemented at the local end on an inexpensive FPGA using no high speed transceivers. The protocol uses a 10-bit LVDS serializer and deserializer, operated at a data rate around 400--660 Mbps, and a local clock source on the FPGA board at the remote end. The FPGA at the local end runs on an independent clock source, and can easily handle multiple optjtag ports in applications where many remote FPGA boards have to be programmed. The discrete devices are chosen to be at least more radiation tolerant that a typical optical transceiver module. We developed a test board to demonstrate the function, and present a couple of future applications.
Speaker: Mikihiko Nakao (KEK) -
60
Portable codeless high-speed interlock logic controller
The interlock system is in charge of the supervision and control of all components from potential accidents.At present, the interlock systems of each plant system are mostly implemented based on PLC, with a response time in the range of 10ms, and the interlock logic has been fixed. However, with the development of experimental requirements, new equipment and new plant systems with new interlock subsystems need to be added.
In the process of designing new interlock logic relationships and setting thresholds, parameters need to be frequently changed and logic relationships need to be frequently debugged, professional interlock control personnel are also required during the whole project. The portable codeless high-speed interlock logic controller designed in this article is a solution specifically designed for sub-millisecond high-speed acquisition and control, while requiring frequent changes in control logic project. It has 400MHz processor, 512MB storage and 256MB running memory, provides 16-channel AI, 4-channel AO, and 28-channel DIO. Suitable for medium-scale logic control (basic control logic quantity 50) applications. Users do not need programming skills, and they only need to use text language to edit logic in software such as spreadsheets. Statement such as: if AI0 > 2.3 or AI3 ≤0.4 then set AO1 = 2.34 set DO0 = 1, the controller will perform the corresponding logical functions.
Users can change the operation logic of signal I/O through text editing without programming, and realize customized logic operation and control output, which can greatly reduce the workload of system debugging and use.Speaker: Zuchao Zhang -
61
Preliminary Design of a General Electronics Platform for Accelerator Facilities
Many accelerators require considerable electronic systems for early tests and verification. In Shenzhen Superconducting Soft X-ray Free Electron Laser (S3FEL), for example, we classify electronic systems into accelerator and beamline categories. The accelerator category includes laser systems, microwave systems, beam measurement systems, magnetic power supply systems, etc., while the beamline category includes optical and diagnostic systems, experimental station systems, etc. The requirements of these systems include analog or RF signal conditioning, waveform digitization, microwave control, motor control, etc. To meet the early tests and verification of various systems, save development expenses, and improve the reusability of hardware, firmware, and software systems, we have considered the needs of each system and preliminarily designed a general electronics platform based on MTCA.4. The Advanced Mezzanine Card (AMC) will place an FPGA Mezzanine Card (FMC) that supports 500 MSPS to 2 GSPS ADC/DAC. We will design two FMC cards on the Rear Transition Module (RTM), which can be used for analog signal conditioning and waveform digitization by 10 MSPS to 250 MSPS ADC/DAC or motor control. The commercial MCH, CPU, power module, and MTCA crate are deployed. This platform can also be applied to other accelerator facilities.
Speaker: Dr Jinfu Zhu (Institute of Advanced Science Facilities, Shenzhen) -
62
Preliminary Design of Data Exchange Module with USB and QSFP Interface for Test of Readout Electronics
The amount of data generated by modern large-scale scientific instruments is tremendously vast, and the efficiency of data retrieval is of utmost importance. The FT601 is a high-performance USB3.0 to FIFO bridge chip, which can be utilized in applications that require high data throughput, such as multi-channel FIFO ADC or DAC devices. This paper presents the design of a circuit board that enables the transmission of data from a QSFP interface to a PC via a Type-C interface, based on the FT601 and Xilinx Artix-XC7A35T FPGA. The Type-C interface adheres to the USB3.0 protocol, with a data throughput of up to 5Gbps. The design of the data transmission board and its performance test results are discussed in this paper.
Speaker: Mr Qiutong Pan (Tsinghua University) -
63
PREVALENCE AND CLINICAL CHARACTERISTICS OF TRANSTHYRETIN CARDIAC AMYLOIDOSIS AMONG HEART FAILURE WITH PRESERVED EJECTION FRACTION
Transthyretin cardiac amyloidosis (ATTR-CA) is an increasingly recognized cause of heart failure. This study aimed to identify the prevalence and characteristics of ATTR-CA among heart failure with preserved ejection fraction (HFpEF). A prospective single-center study included patients aged > 65 years with a diagnosis of HFpEF (EF >50%) between November 2021 and December 2022. A total 124 patients were included (median age 82.9 years, 78% male) was conducted. Clinical, analytical, and diagnostic imaging data were collected. Visual grading was evaluated with 99mTc-DPD bone scintigraphy. ATTR CA was diagnosed by positive scintigraphy (Perugini grade 2 or 3) and exclusion of light-chain amyloidosis or positive biopsy typing. ATTR-CA prevalence among HFpEF was 9.7% (12/124). AATR-CA patients were older (p=0.0019) and had higher values of septal wall thickness (p=0.001), posterior wall thickness (p<0.001), left ventricular mass index (p=0.021), relative wall thickness (p<0.001), and N-terminal pro-B-type natriuretic peptide (NT-proBNP, p<0.001). On the other hand, there was no significant difference in Agent Orange exposure history, body mass index, presence of hypertension, diabetes, hyperlipidemia, atrial fibrillation, heart rate, left ventricular EF, stroke volume, left ventricular mass, ratio of peak velocity of early diastolic transmitral flow to peak velocity of early diastolic mitral
annular motion, and estimated glomerular filtration rate values. This study identified a higher prevalence of ATTR-CA in HFpEF than in the general population. Additionally, these patients tended to have thicker
ventricular walls, higher LV mass index, and higher levels of NT-proBNP. We should realize that ATTR-CA may be one cause of HFpEF.Speaker: Ms Miju Cheon (Veterans Health Service Medical Center) -
64
Primary results of cosmic-ray recognition for a Plastic Scintillation Detector Using Machine Learning
This study explores the application of machine learning, specifically a one-dimensional Convolutional Neural Network (1D CNN), to differentiate the signals from cosmic rays from those of background when using a single plastic scintillation detector. A comprehensive dataset, combining signals from cosmic ray and gamma events, was collected for the machine learning approach. The 1D CNN model, constructed using the Keras library with TensorFlow as the backend, was compiled with precision, utilizing the Stochastic Gradient Descent (SGD) as the optimizer and the sparse_categorical_crossentropy as the loss function. The proposed model achieved promising results, demonstrating its ability to reliably distinguish between the signals of cosmic-ray and gamma events.
Speaker: Nguyen Tri Toan Phuc (University of Science - Vietnam National University-Hochiminh City) -
65
Readout Electronics for a Prototype TPC-based MeV Gamma-ray Telescope
A design of readout electronics for a prototype electron-tracking Compton camera has been developed recently. The Compton camera will be a high-resolution MeV gamma-ray telescope in space. The telescope comprises a 30 cm cubic gaseous time-projection chamber (TPC) for electron tracking and energy measurement, with a $40 ~\mathrm{mm} \times 40 ~\mathrm{mm} \times 10 ~\mathrm{mm}$ spatial-sensitive, high-resolution cadmium zinc telluride (CZT) detector array at the bottom of the TPC for scattering gamma-ray detection. To improve the spatial and energy resolution of electrons, a $\mathrm{30 ~ cm \times 30 ~ cm}$ Micromegas detector with two-dimensional 0.65 mm pitch strip anodes has been used as the anode plane of TPC. The CZT detectors have pixelated anodes for the same purpose. Each CZT detector has $11\times11$ pixelated anodes with a 1.72 mm pitch. Four detectors have been used in total. Therefore, two kinds of different front-end electronics with different ASICs are used to process signals from TPC and CZT detectors separately and finally collected by the data acquisition system. We have conducted the performance test of a single CZT detector. The results show that the energy resolution of most pixels is better than 2% at 662 keV, which can satisfy the demand for resolution of the angular resolution measure (ARM) of incident gamma rays.
Speaker: Mr Maoyuan Zhao (University of Science and Technology of China) -
66
Real-Time Cross-Coupling removal and Monitoring in RF feedback systems: HLS-based FPGA implementation
Implementing digital signal processing (DSP) solutions on FPGAs is a challenging task that requires technical knowledge of the system and the functionality of algorithms. Using High-Level Synthesis (HLS) tools for handling DSP tasks accelerates the implementation process and reduces the development stage. Moreover, HLS solutions decrease FPGA verification time and provide flexibility for configuring design parameters with extensive iteration capabilities. In this paper, hardware accelerator units are introduced to correct the driven Radio Frequency (RF) signals in Low-Level RF (LLRF) multi-cavity controller systems. In RF stations, a portion of the injected signal into cavities is reflected due to the mismatch in the frequency of the forward signal and the resonance frequency of cavities. The presented design improves the forward signal in multi-cavity stations by real-time removal of the cross-coupling effect from the signal. This is achieved using the concepts of pipelining, parallelism, and the proper usage of FPGA resources for DSP calculation. Moreover, the paper introduces a real-time monitoring system for RF systems. Proposed units are used for detecting anomalies in the system by comparing the actual probe signal from each station with the virtual probe calculated based on the input signal. The main benefits of this solution are real-time calculation of corrected signals using DSP techniques and the introduction of an anomaly detector. Furthermore, this design reduces the workload from other parts of the system with off-load correction and monitoring of the RF cavities, leading to better performance of the overall system.
Speaker: Nima Omidsajedi (DESY) -
67
Real-time reconstruction of plasma density profile based on deep neural network
In magnetic confinement fusion devices, e.g., Tokamak, plasma position measurements play an important role in the safety protection and the prevention of disruption. Plasma density profiles can be used as important reference for calculating plasma positions. Therefore, real-time reconstruction of plasma density profiles has been attempted by many researchers. In this paper, a deep neural network is used to process microwave reflectometer measurement data and reconstruct the density profile in real time. The input layer of the deep neural network has 10,000 nodes and accepts in-phase (I) and quadrature (Q) data from microwave reflectometer measurements. The encoder of the network is a Multi-Layer Perceptron (MLP), and the decoder uses a Transformer model based on a self-attention mechanism. The MLP contains two hidden layers. Each hidden layer includes a linear operation layer and a nonlinear operation layer using the ReLU nonlinear activation function. The encoder extracts from the input data through nonlinear mapping. The Transformer decoder further decodes these features and generates the final reconstructed plasma density profile through the linear output layer. Compared with algorithms using classic neural networks, deep neural networks have significantly improved training efficiency, calculation speed, and reconstruction accuracy.
Speaker: Dr Fei Wen (Institute of Plasma Physics,Hefei Institutes of Physical Science,Chinese Academy of Sciences) -
68
ROOT-based general online data visualization system
The online data visualization system is an essential component of the data acquisition system, delivering swift, efficient, and comprehensive real-time monitoring for detectors and readout electronics. Simultaneously, ROOT, an open-source software framework for data analysis in high-energy physics, provides a variety of data analysis tools. Utilizing ROOT-based online histogram monitoring, researchers can efficiently analyze data in real-time and promptly detect potential anomalies. To minimize development costs and enhance deployment efficiency, a general online data visualization system based on ROOT has been designed and implemented. This system comprises configuration module, data readout and decoding module, and data display module. Each module offers specific interfaces for seamless integration and expansion. Additionally, the system takes advantage of file-based configuration management for minimal modifications when interfacing with different experiments. Currently, the system offers data source interfaces supporting Redis and Kafka, as well as histogram interfaces supporting one-dimensional and two-dimensional histograms. It has been successfully employed in joint testing for different projects, facilitating efficient and convenient data monitoring. The detailed design, implementation, and application of the system will be presented in this talk.
Speaker: Shuihan Zhang (Institute of High Energy Physics, CAS) -
69
SPLENDAQ: A Detector-Agnostic Data Acquisition System for Small-Scale Physics Experiments
Many scientific applications from rare-event searches to condensed matter system characterization to high-rate nuclear experiments require time-domain triggering on a raw stream of data, where the triggering is generally threshold-based or randomly acquired. When carrying out detector R&D, there is a need for a general data acquisition (DAQ) system to quickly and efficiently process such data. In the SPLENDOR collaboration, we are developing the Python-based SPLENDAQ package for this exact purpose - it offers two main features for offline analysis of continuous data: a threshold-triggering algorithm based on the time-domain optimal filter formalism and an algorithm for randomly choosing nonoverlapping segments for noise measurements. Combined with the commercially available Moku platform, developed by Liquid Instruments, we have a full pipeline of event building off raw data with minimal setup. Here, we review the underlying principles of this detector-agnostic DAQ package and give concrete examples of its utility in various applications.
Speaker: Samuel Watkins (Los Alamos National Laboratory, USA) -
70
Status and further development of the Tirgger Time Event system for fusion experiment Wendelstein 7-X
Since the first plasma operation in 2015, the superconducting fusion experiment Wendelstein 7-X has successfully completed 4 experiment campaigns (OP1.1, OP12a, OP1.2b, and OP2.1). The current machine maintenance phase will be completed end of 20232, followed by the commissioning of W7-X. The scientific plasma operation phase OP2.2 is planned from June 2024.
The Trigger Time Event System is used by the control and data acquisition systems of the central control systems, the technical components and the diagnostics of W7-X for their time synchronization, for processing events and for generating and receiving trigger signals. This use cases makes it necessary to adapt the TTE system to the changing requirements of users.
After an introduction to the functions and structure of the TTE system, this contibution describes the current expansion status of the TTE system and the planned modifications and expansion of the hardware and software of the TTE system. Finally, the current status of the planned work on the TTE system for the upcoming W7-X operational phase Op2.2 is presented. The article ends with a summary.Speaker: Jörg Schacht -
71
STUDY OF MODIFICATION SOLUTIONS IN THE MEANDERING RIVER WITH ALLUVIAL GROUND ALONG THE TIEN RIVER FLOWING THROUGH SA DEC - CAO LANH – CHAU THANH
The Tien River flowing through the area of Sa Dec - Cao Lanh - Chau Thanh in Dong Thap Province, covering a stretch of approximately 22 kilometers, is a meandering section with dangerous erosion on the Tien and Hau River system, along with alluvial ground developing in river changing the flow. The development of alluvial ground combined with fish raft farming and sand exploitation has led to severe erosion of the riverbed and banks in the Binh Hang Tay and An Hiep communes, causing psychological instability for the local people and local authorities. The content of the study introduces modification solutions for natural, environmentally friendly bank adjustment, in which dredging alluvial ground to widen the riverbed helps reduce the flow pressure pushing against the concave banks. The modification solutions indicate a significant reduction in erosion along the concave bank. Calculation results show that proactively widening and dredging the alluvial ground with an appropriate scale can reduce riverbed erosion by 1 ÷ 2 m after 6 years and change the river flow in a rational way to effectively reduce erosion. The solution involving dredging and sand exploitation with a reasonable scale not only reduces erosion but also saves costs while utilizing sand resources for other construction projects. However, this dredging solution requires time for stable adjustment, strict monitoring, management of alluvial ground development, dredging and mining of resources in a rational manner.
Speaker: Mrs Thi Nhan Truong (Institute of Coastal and Offshore Engineering) -
72
Study on Readout Electronics of CEPC Scintillator Analog Hadronic Calorimeter Prototype
Circular electron positron collider (CEPC) is proposed to research Higgs and particle flow algorithm (PFA) is expected to be adopted to get a high energy resolution. As a PFA calorimeter, CEPC hadronic calorimeter (HCAL) has the feature of fine granularity, which raise demands of high integration, low noise and low power consumption to the readout electronics. The scintillator analog hadronic calorimeter (Sc-AHCAL), which is one of PFA HCAL technical routes, has been studied. In this paper, a readout system of CEPC scintillator AHCAL prototype is designed and implemented. The system can not only readout the signals of high-density SiPMs, but also has functions such as electronic self-check, gain monitoring, and temperature compensation. And the beamtest proves the system performs well.
Speaker: Mr Zhongtao Shen (University of Science and Technology of China) -
73
Study on the Timing Performance of the SiPMs
Silicon Photomultipliers (SiPMs) are new type of high-performance semiconductor detectors, which inherit most of the advantages of semiconductor detectors and have good performance in terms of gain, signal-to-noise ratio and response speed. SiPM also has high photon detection efficiency and excellent time resolution, which is comparable to high-performance PMT. This manuscript tested the timing characteristics of three types of SiPMs (Hamamatsu, SensL and NDL). The rise time of SensL J-30035 fast output port can reach 500 ps, the limit time resolution is 22.2 ps. The rise time of DNL SiPM model 11-3030C-S is 1~2 ns, and the limit time resolution is 21.8 ps. The rise time of Hamamatsu SiPM model S13360-1325CS is 1~2 ns, and the limit time resolution is 193.6 ps. Therefore, SensL J-series SiPMs have the best timing characteristics.
Speaker: Sen Qian -
74
The data acquisition system of WEST’s New Thomson Scattering diagnostics
WEST, the Tungsten Environment Steady state Tokamak at IRFM (France), is currently being equipped with two new plasma-monitoring systems based on Thomson Scattering. The intensity and spectrum of the scattered fraction of photons of an incident LASER pulse holds information on the density and temperature of electrons in the plasma, which are two essential parameters for plasma physics and real-time plasma control. Nearly fifty optical viewing lines will be installed to collect diffused light near the core plasma region and in the plasma pedestal. This contribution will describe and discuss the performances of the real-time data acquisition and processing system to which the collected pulses of Thomson scattered light are propagated. Classically, it consists of one polychromator and one Nectarine data acquisition board for each viewing line, all located in thermo-regulated cubicles. The Nectarine board is a custom design adapted to the polychromators : it provides six triggered fast channels to catch the scattered pulse shape at a minimum of 1 GS/s thanks to three Nectar chips. Six further ADC channels are provided for background monitoring at a slower rate (100 KS/s). Nectarine was designed as a baseboard for a Microzed, Avnet’s open source System On Module based on Xilinx’s Zynq SoC. The Zynqs are in charge of system configuration and control thanks to the embedded firmware and standalone lwip TCP/IP clients and of data readout and transfer to the backend PC via UDP. The backend runs a TCP/IP and UDP server within the WEST framework.
Speaker: Christophe Bouchand (CEA-Cadarache IRFM) -
75
The Design of an 8-channel, 41.7-ps Resolution Time-to-Digital Converter for STCF ECAL
The Super Tau-Charm Facility (STCF) under construction in China demands for a new Electromagnetic Calorimeter (ECAL) with good time measuring capability to realize background suppression and gamma-neutron discrimination. The time measurement requirements include high resolution, large dynamic range and multi-channel integration. Therefore, we adopted a 3-level-structure based Time-to-Digital Converter (TDC) which can realize large dynamic range with a coarse counter as the first level and high resolution with a modified Vernier Delay Loop (VDL) as the finest level. The proposed VDL can get a stable and sub-gate resolution utilizing differentials between two kinds of unit delay locked by different Delay Locked Loops (DLLs). The proposed VDL is also characterized with the cyclic structure for linearity improvement and the automatic restoration for continuous measurement. The proposed 8-channel TDC was fabricated with standard 180-nm CMOS process and it can reach a resolution of 41.7-ps and dynamic range of 2.56-μs under the reference clock frequency of 100-MHz. According to test results, the precision of asynchronous measurement is 47.0-ps in the best situation and all channels have good linearity with DNL < 1 LSB and INL < 1.5 LSB.
Speaker: Dr Ziwei Zhao (School of Computer Science and Technology, Northwestern Polytechnical University) -
76
The Design of Hardware Accelerator for Compute-Intensive Tasks in Solving Neutron Transport Problems by Method of Characteristics
The Method of Characteristics (MOC) has been proved as an effective method to solve many-group neutron transport problems for full core Light Water Reactor (LWR) analysis. The method has been widely used to solve 2D lattice physics problems due to its ability to provide high accuracy solutions to problems with geometric details. Due to the computational and memory expensive of solving full core many-group neutron transport by 3D MOC, efforts have been focused on 2D/1D coupling methods which solve 3D problems as a coupled system of 2D MOC solver for radial planes and other deterministic solver for 1D axial columns. With today’s widely availability of massively multi-node, multi-core computers together with computational hardware such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), and Application-specific Integrated Circuit (ASIC) to accelerate high-cost computations, using 3D MOC to solve full core many-group neutron transport problem for LWR analysis is feasible. This presentation describes the design and implementation of a hardware accelerator for compute-intensive operations in MOC. The implementation can be used for both 2D and 3D MOC solvers since the design is independent from problem geometry and dimension. Each accelerator can be installed in each node of a multi-node system to handle the high-cost computations where the node CPU handles low-cost computations and processes such as geometry construction, track generation, ray tracing, node communication, input/output processing, etc. The design has been implemented and synthesized with several different technologies. The results demonstrate that the design yields good computational speed with desired accuracy.
Speaker: Prof. Thuy Le (San Jose State University) -
77
The effects of the dead layer thickness increase to the regions in the spectrum response for a coaxial HPGe detector
In the work, we studied the influences of dead layer thickness on the whole gamma
spectrum response for HPGe detector by using Monte Carlo simulation. From the
simulated relation of the FEPEs and the dead layer thicknesses, the dead layer thickness
of 0.567 mm was derived which increased compared with the nominal value of 0.46 mm
from manufacturer after 4 years of operation. The multiple scattering region and peak
decreased with different rates and the valley region of the forward scattering photon
increased quickly when the dead layer thickness increased. The energy dependence of the
P/T and the general range were also carried out. The results showed that the effect of the
increase in dead layer thickness on regions in the spectrum was not the same. Through
this study, among several scintillators, it was possible to find a HPGe detector suitable for
the purpose of the studySpeaker: Đạo (K.Y) Nguyễn Quang (Department of Biomedical physics - Faculty of Medicine - Nguyen Tat Thanh University) -
78
The Ethernet readout of the DUNE DAQ system
In 2023 the Deep Underground Neutrino Experiment (DUNE) Data Acquisition (DAQ) system transitioned to the new Ethernet based readout. The adaption of the Ethernet protocol mainly required integration aspects to the available generic and modular readout subsystem. This work includes a completely new I/O device library implementation, interfacing with the detector electronics via a firmware block that is provided by the DAQ, and the frame unpacker of the Trigger Primitive Generation (TPG) utilizing the new detector electronics data format. In order to sustain the multiple 100 Gb/s aggregated input data streams’ high-throughput and low latency requirements, the new software stack for the I/O device control, configuration, monitoring and readout of Network Interface Controllers (NICs) is built upon the Data Plane Development Kit (DPDK). This framework and set of libraries support routing capabilities based on configurable rules that the DAQ heavily relies on for load-balancing purposes. With this feature the readout splits up the aggregated 100 Gb/s link to the resulting individual data streams, that are passed down to their corresponding processing pipelines for trigger primitive generation and buffering. Extensive monitoring capabilities are also provided by the library, which monitors errors related to data consistency and integrity, and also aids the performance optimization work of the software stack.
In this contribution we describe the new high-throughput Ethernet based readout integrated to the DUNE DAQ system, and the first performance optimizations and results using the ProtoDUNE experiments hardware apparatus at the Neutrino Platform at CERN.
Speaker: Roland Sipos (CERN) -
79
The full scale prototype of the PIP-II dedicated RFPI system
The Radio Frequency Protection Interlock safety system is integral to the modern accelerator infrastructure. It is responsible for instantaneous RF signal permits drop in case of sudden cavities operation conditions violations.
Information about the cryogenic system status, coupler bias high voltage and current, electron pick-up current level, temperatures, RF signal leakage, LLRF system status, and cavity RF signals levels are, among others, input signals to this safety system. Different signal types require various input conditioning stages. Regardless of the initial form of each entry, all monitored values are transferred to the digital representation and compared with safety margins. The FPGA-based main logic unit uses these limits to detect faults in the system and to disable output permits immediately therefore stopping the cavity operation with RF power.
After the successful design and evaluation of the proof of concept prototype, the next iterations of the RFPI project took place. The full-scale prototype has been proposed and designed. The contribution discusses a new setup that can be configured to protect up to four cavities at the same time. The updates and modifications to the PoC design including different SoC module usage, signal conditioning modules redesign into double FMC form, and configuration flexibility improvements are being discussed. Moreover, the initial evaluation of the system components' performance results is presented.Speaker: Dr Wojciech Cichalewski (LUT) -
80
The study of calibration process for the dual-threshold hybrid pixel array detector of HEPS-BPIX40
Abstract: This article introduces the calibration process of the upgraded version HEPS-BPIX40 of the hybrid array pixel detector HEPS-BPIX designed for the China High Energy Synchrotron Radiation Source. The detector consists of 40 detection modules spliced together to form an approximately 6M pixel array, and has achieved a key improvement from measuring X-rays of one energy to measuring X-rays of two energies simultaneously. Based on the new measurement requirements, a dual-threshold scan was performed, the relationship between energy and threshold was quantified, and dual-threshold calibration was performed. For the threshold fine-tuning of dual thresholds, an accurate algorithm based on LDAC characteristics is introduced, and the mutual influence between dual thresholds and the differences between chips are studied. Under the precise algorithm, adjusting the difference between chips successfully reduced the dead pixel rate to 0.01%; while without adjusting the difference between chips, the dead pixel rate could only be reduced to 0.05%. Through this series of work, HEPS-BPIX40 has made significant progress in large-scale pixel count and dual threshold scale, providing new technologies and methods for cutting-edge research in the field of high-energy synchrotron radiation light source detection.
Speaker: Ms Xueke Ma (1.Shaanxi University of Science and Technology, Xian China 710021) -
81
Time-based electronics for T-SDHCAL
SDHCAL (Semi-Digital Hadronic Calorimeter) is a highly granular hadronic calorimeter based on PFA (Particle Flow Algorithms). A prototype of SDHCAL was completed and tested in 2011 and 2012.
The idea of T-SDHCAL (T for Timing) is intended to gain better reconstruction of particle energy. High resolution timing technics can help separate close-by showers and reduce the confusion for a better PFA application.
On behalf of SDHCAL group in Shanghai Jiaotong University, the work I want to present is to develop a high-resolution timing electronic system for T-SDHCAL. It is a system that can be generally applied to mRPC readouts. This system is based on Petiroc-2B, an ASIC developed by OMEGA. We have built a prototype with 2 Petiroc, 64 channels. The work includes PCB design, FPGA programming, data transfer based on ethernet, etc. We have completed injection tests, which validates the design of the system and the timing resolution is under 50ps, meeting the requirements of T-SDHCAL.
The next step of our work is to complete beam tests with mRPCs, and build a large-sized (1m*1m) prototype.Speaker: Yongqi Tan (Shanghai Jiaotong University) -
82
Verification and Validation of Real-Time Diagnostics for the KSTAR Plasma Control
Verification and Validation of Real-Time Diagnostics for the KSTAR Plasma Control System
R. Ramon 1, K. Erickson 1, M. Podesta 1, J. Yoo 1,
Steve SABBAGH 2,
J. Bak 3, W. Ko 3, M. Choi 3, J. Lee 3, and K, D. Lee 3
1PPPL, USA, 2Columbia University, USA, 3KFE, Korea-
Princeton University Plasma Physics Laboratory, NJ, USA
-
Email address: reedrm@pppl.gov
Abstract
The KSTAR (Korea Superconducting Tokamak Advanced Research) DPA (Disruption Prediction and Avoidance) project led by Steve Sabbagh and Columbia University established a need for increased real-time diagnostic inputs to the KSTAR PCS (plasma control system) to support the real-time evaluation of DECAF (Disruption Event Characterization and Forecasting) algorithms.
Test cases need to be developed for the DPA project for KSTAR.
Since KSTAR's PCS and D3D's PCS are related, leveraging D3D's PCS knowledge helps to develop test cases for KSTAR. D3D has a regression testing tool that checks to see if any changes in the candidate branch breaks any existing software. This is key to producing progressive codes for research on an ongoing basis without resorting to live testing during operations.The test cases have to collect input data from 433 channels ranging from a high data rate of 500 kHz to 1kHz.
The Input data consists of: (192) (ECEI) analog signals, (128) (ECE) analog signals, (1) 512x512 image (VPhi), (16) MHD analog signals, and (96) MHD digital signals.<Please see the the enclosed file for the full abstract>
Speaker: Ramon Reed (Princeton University Plasma Physics Lab) -
-
83
Virtualizing experimental setups based on GATE/GEANT4 Monte Carlo simulation results
The Monte Carlo simulation toolkit is widely used for simulating particle interactions and propagation through matter, particularly in medical imaging and radiation therapy experiments. The display of the GATE/GEANT4 simulation configuration highly depends on the operating system. This study aims to develop a web-based tool where users can quickly view the simulation configuration through a web browser. The tool is built using HTML, CSS, and JavaScript programming languages. Additionally, the 3D visualization of the experimental setup is constructed using the three.js and ROOTJS libraries. The tool supports users in modifying parameters, viewing configurations, and updating the GATE/GEANT4 macro. The web-based simulation configuration visualization tool helps users quickly survey experimental setups and reduces dependence on specific devices.
Speaker: Hoang Thi Kieu Trang (University of Science, Ho Chi Minh City, Vietnam)
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24
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12:55
Lunch
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Oral presentations
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84
Reconstruction of pile-up events using an Autoencoder based on CNN for the NEDA detector array.
Pulse pile-up poses an issue in the study of nuclear reactions and spectroscopy, arising when two pulses overlap, distorting data and compromising the accuracy of energy and timing details. Various digital and analogue techniques have been used to deal with pile-up interference. However, some pile-up events may include interesting pulses that require reconstruction.
This study introduces a novel approach to reconstructing pile-up events acquired using the Neutron Detector Array (NEDA), employing an Autoencoder based on a Convolutional Neural Network (CNN). The training and testing datasets for the Autoencoder have been created from NEDA data.
This new pile-up signal reconstruction method has been evaluated considering the similarity between reconstructed signals and the originals. Furthermore, it has been analysed from the point of view of Charge Comparison (C.C.), comparing the result obtained from original and reconstructed signals. The results of the analysis showcased a high similarity between the original and reconstructed signals, with an average correlation of 0.988, and 85.53% success in identifying particles post-reconstruction. This technique holds promise in mitigating adverse effects of pulse pile-up, salvaging previously discarded valuable information, and empowering future high-count-rate nuclear reaction and nuclear spectroscopy studies.Speaker: Jose Manuel Deltoro Berrio (Universitat de Valencia) -
85
Machine Learning for Sub-Microsecond Edge Data Processing
The improvements in artificial intelligence, particularly the many flavours of Machine Learning (ML), add a powerful and versatile tool to data acquisition (DAQ) strategies. However, large and deep neural networks remain memory and compute intensive, limiting their usability at the edge. One of the most important aspect of integrating ML in a DAQ system is determining when and where integrating a machine learning
algorithms will be most beneficial and how to minimize the model size without losing the precision and accuracy required for a scientific application.We designed and tested a DAQ integrating ML for the CookieBox, a detector capable of sampling an x-ray shot from LCLS-II and determining its suitability for an experiment. By moving the analysis to the edge, this detector can now be used to veto x-ray shots in real-time and reduce the overall data collected for an experiment. The analysis is completed in 0.4 us with an accuracy of 84~% using a few watts of power.
In this talk, we will share insight on the choices made to minimize the ML footprint, implement the data preprocessing and optimize the latency. In addition, we will present the validation methods we used and how our edge ML compares to offline methods.
Speaker: Prof. Audrey Corbeil Therrien (Université de Sherbrooke) -
86
A QGP Trigger for the CBM Experiment based on Artificial Neural Networks
The field of heavy-ion experiments, such as the future Compressed Baryonic Matter (CBM) experiment at FAIR, necessitates algorithms that are high in performance and efficient in real-time data analysis. The increasing integration of machine learning techniques, particularly artificial neural networks, into physics experiments marks a significant advancement in this domain. The report introduces the application of a specialized neural network package, ANN4FLES, which has been optimized for high-performance computing clusters. The primary focus of this study is the utilization of ANN4FLES in the CBM experiment for the detection and classification of events indicative of Quark-Gluon Plasma (QGP) production.
Our research presents an advanced approach using ANN for developing a QGP trigger within the First Level Event Selection (FLES) package, integral to the CBM experiment. The investigation involves the use of both fully-connected and convolutional neural networks. These networks are trained and tested on simulated data of Au+Au collisions at 31.2A GeV, generated using the Parton-Hadron-String Dynamics (PHSD) off-shell transport model. Our research demonstrate that the convolutional neural network model notably surpasses the performance of fully-connected networks, achieving an impressive accuracy rate of over 95% on the testing dataset.
This report delves into the nuances of the neural network's superior selection efficiency, exploring the intricate physics that underlie this high rate of accuracy in identifying events featuring QGP. Additionally, we discuss various essential characteristics of neural networks, particularly in the context of their application to the selection process in heavy ion collisions where quark-gluon plasma production is a significant factor.
Speaker: Prof. Ivan Kisel (Uni-Frankfurt, FIAS, GSI, HFHF) -
87
hls4ml: low latency neural network inference on FPGAs
Machine learning is becoming increasingly prevalent in High Energy Physics (HEP), offering significant potential for enhancing trigger and Data Acquisition (DAQ) performance, as well as other real-time control applications. However, the exploration of these techniques in low latency/power Field-Programmable Gate Arrays (FPGAs) is still in its early stages. We introduce hls4ml, a user-friendly software based on High-Level Synthesis (HLS), designed specifically for deploying network architectures on FPGAs. To demonstrate the features of hls4ml we will show several case studies at the Large Hadron Collider (LHC) and analyze resource usage and latency in relation to different network architectures. Additionally, we report on the progress of new developments in hls4ml, particularly focusing on newer neural network architectures graph neural networks, transformers, symbolic regression, support for QONNX and discuss their potential for use in future HEP applications and beyond.
Speaker: Vladimir Loncar (Massachusetts Inst. of Technology (US)) -
88
Development of ML FPGA filter for particle identification and tracking in real time
With the increase of luminosity for accelerator colliders as well as a granularity of detectors for particle physics,
more challenges fall on the readout system and data transfer from detector front-end to computer farm and long term storage.
Modern concepts of trigger-less readout and data streaming will produce large data volumes being read from the detectors.
From a resource standpoint, it appears strongly advantageous to perform both the pre-processing of data and data reduction at earlier stages of a data acquisition.Real-time data processing is a frontier field in experimental particle physics.
Machine Learning methods are widely used and have proven to be very powerful in particle physics.The growing computational power of modern FPGA boards allows us to add more sophisticated algorithms for real time data processing.
Many tasks could be solved using modern Machine Learning (ML) algorithms which are naturally suited for FPGA architectures.
The FPGA-based machine learning algorithm provides an extremely low, sub-microsecond, latency decision and makes information-rich data sets for event selection.Work has started to develop an FPGA based ML algorithm for a real-time particle identification and tracking with Transition Radiation detector and E/M Calorimeter.
This report describes the progress in building the ML-FPGA test setup.
Speaker: Sergey Furletov (Jefferson Lab, (US)) -
15:30
Coffee Break
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89
High-speed data processing in the RIBF DAQ system using the Alveo data-center accelerator card
High-speed data processing in DAQ using hardware accelerators such as GPU and FPGA has been gaining attention to accommodate the increasing intensity of accelerator beams. We have been investigating the possibility of implementing such hardware accelerator devices for the DAQ system at RIKEN RIBF. Alveo U50 is one of the series of data center accelerator cards provided by Xilinx, which contains an AMD Ultrascale+ FPGA chip with 8GB HBM (high-bandwidth memory). The board supports PCI Express for installation in typical workstations or computing servers, as well as 100Gbps connectivity with a QSFP28 port. Using the Alveo U50, we have implemented the particle identification algorithm for the BigRIPS fragment separator and succeeded in reproducing the results obtained with the typical offline analysis software. In particular, the data processing throughput exceeds that of CPU, even though the C++ codes are automatically converted to RTL by high-level synthesis without any manual tuning of the RTL design. We see potential in this scheme and are exploring the possibility of further applications. In this contribution, we will present the current status of this project and future prospects.
Speaker: Yuto Ichinohe -
90
Readout system for a strip ionization chamber dedicated for proton beam profile measurement
This work presents a 448-channel readout system integrated into a multi-strip ionization chamber for proton beam profile measurements. Miniaturized current-input ADCs inside the detector vessel provide direct digitization of charge collected on 1.5mm cathode strips. An FPGA configures ADCs dynamically and handles acquisition triggering and data processing, enabling real-time beam analysis. This compact, flexible architecture achieves sub-millimeter spatial discrimination across the 420mm x 320mm area for efficient beam parameter quantification.
Speaker: Ye Lin (Shanghai Advanced Research Institute, CAS) -
91
DAQ system for CEPC Vertex detector prototype
Abstract: The discovery of the Higgs boson was a significant milestone in the history of particle physics. In pursuit of more precise measurement of the Higgs boson’s properties and interactions, Chinese high-energy physicists proposed the Circular Electron Positron Collider (CEPC) project. The silicon pixel vertex detector, which requires high spatial resolution, low material budget, and radiation hardness, is one of the major technical challenges in the CEPC’s preliminary research. Development of CMOS pixel sensors and a silicon pixel detector prototype have been carried out to satisfy the requirements of CEPC vertex detector. Data Acquisition System (DAQ) is an essential component of the silicon pixel detector experiment. To meet the requirements of the silicon pixel detector prototype, a specialized data acquisition system was designed and implemented.
The DAQ system is designed to configure readout electronics and pixel detector sensors, read out data continuously from the electronics boards, verify the data format, and subsequently store the data on a disk. In addition, the system includes a graphical user interface (GUI) that facilitates run control and monitoring, and periodically updates the hit-map. The system’s software is developed in Java, with the graphical interface being crafted in JavaFX.
The software has undergone rigorous testing in the laboratory and has been validated during test beam experiments of DESY. The results demonstrate that the software performs reliably and fulfills the data acquisition requirements for the detector prototype.Key Words: Data acquisition system, Silicon pixel vertex detector, Data flow, User interaction
Speaker: Chang Xu -
92
FERS-5200: a distributed Front-End Readout System for multidetector arrays
The FERS-5200 is the new CAEN Front-End Readout System, answering the challenging requirement to provide flexibility and cost-effectiveness in the readout of huge detector arrays. FERS-5200 is a distributed and easy-deployable platform integrating the whole readout chain of the experiment, from detector front-end to DAQ. It is based on compact ASIC-based front-end cards integrating A/D conversion and data processing, which can be ideally spread over a large detector volume without drawbacks on the readout performance. Synchronization, event building and DAQ is managed by a single Concentrator board, capable of sustaining thousands of readout channels. Using the appropriate Front-End, the solution perfectly fits a wide range of detectors such as SiPMs, multianode PMTs, GEMs, Silicon Strip detectors, Wire Chambers, Gas Tubes, etc, thus matching the requirements of different applications
Speaker: Dr Carlo Tintori (CAEN SpA) -
93
Simplified Firmware Development for Open FPGA Platforms in DAQ Systems using SciCompiler
In the realm of modern trigger and data acquisition (DAQ) systems, the adoption of programmable logic devices underscores the advantages of versatile, reusable mixed-signal platforms, known as open FPGA boards. These boards enable seamless integration of custom processing algorithms into firmware, enhancing their appeal across diverse applications. However, FPGA development languages like VHDL or Verilog for custom logic and readout system development can be daunting. In this presentation, we introduce an innovative approach to simplify firmware development. We present a user-friendly graphical programming interface featuring a catalog of IP cores tailored for nuclear physics applications. This interface allows users to effortlessly connect blocks to implement trigger logic, akin to assembling physical NIM modules. SciCompiler software revolutionizes firmware development, empowering users to create customized readout systems for applications like nuclear spectroscopy, particle imaging, and more. It leverages virtual instruments such as scalers, counters, TDCs, energy filters, and Pulse Shape Discriminators. SciCompiler streamlines processing algorithm implementation and generates essential readout interfaces and libraries for the complete data acquisition chain—from detector to data storage. This streamlined process is further enhanced through the introduction of the new SciSDK library, which facilitates seamless interfacing with compatible SciCompiler hardware using consistent instructions from virtually any modern programming language. It refocuses development on the application, eliminating the need for deep FPGA programming knowledge. Open FPGA boards, with or without ADCs, cater to diverse needs, ranging from single to 128 channels per module with sampling rates up to 5 GSPS.
Speaker: Andrea Abba (Nuclear Instruments SRL)
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84
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18:15
Women In Engineering
Reception and discussion panel at Seagull Hotel
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Invited Talk, Oral presentations, Mini-Orals
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94
End-to-end Codesign of Hessian-aware Quantized Neural Networks for FPGAs
We develop an end-to-end workflow for the training and implementation of co-designed neural networks (NNs) for efficient field-programmable gate array (FPGA). Our approach leverages Hessian-aware quantization (HAWQ) of NNs, the Quantized Open Neural Network Exchange (QONNX) intermediate representation, and the hls4ml tool flow for transpiling NNs into FPGA firmware. This makes efficient NN implementations in hardware accessible to nonexperts, in a single open-sourced workflow that can be deployed for real-time machine learning applications in a wide range of scientific and industrial settings. We demonstrate the workflow in a particle physics application involving trigger decisions that must operate at the 40 MHz collision rate of the CERN Large Hadron Collider (LHC). Given the high collision rate, all data processing must be implemented on custom ASIC and FPGA hardware within a strict area and latency. Based on these constraints, we implement an optimized mixed-precision NN classifier for high-momentum particle jets in simulated LHC proton-proton collisions. In addition, we use a second particle physics example of lossy data compression with an autoencoder for the High-Granularity Endcap Calorimeter subdetector. We report on these two NNs with our end-to-end codesign workflow.
Speaker: Vladimir Loncar (Massachusetts Inst. of Technology (US)) -
95
Science Rate Acceleration with ESnet-JLab FPGA Accelerated Transport Load Balancer
To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define and implement an edge to compute cluster data event load balancing architecture with hardware accelerated elements to address compression, fragmentation, dynamically switched destination transport and reassembly at the event level. A core component is the ESnet-JLab FPGA Accelerated Transport (EJFAT) that functions as a network Forwarding-Plane (FP) in conjunction with an associated control-plane (CP) that handles compute node subscriptions and balances node workloads at the event level based on node feedback. This core load-balancer (LB) provides for three-tier horizontal scaling across (1) multiple FPs, (2) cluster nodes subscribed to an FP, and CPUs within a node. EJFAT effectively provides seamless integration of edge / cluster computing to support direct experimental data processing for immediate use by JLab science programs and others such as the Electron-Ion Collider (EIC) as well as data centers of the future requiring high throughput and low latency for both time-critical data acquisition systems and data center workflows. When completed, EJFAT will have an operational impact for integrated research infrastructure as called for in \cite{b0}, \cite{b1}, \cite{b2}, \cite{b3}, \cite{b4}, \cite{b5}, \cite{b7}, \cite{b8}, \cite{b9}, and \cite{b10}, and currently operates a new load balancing architecture. We report on future plans and experiences to date with cluster node load balancing and science rate acceleration both at JLab and also in conjunction with ESnet and Lawrence Berkeley National Laboratory (LBNL).
Speaker: michael goodrich -
96
Development of the Proton Computed Tomography (pCT) prototype
Proton computed tomography (pCT) is a novel three-dimensional medical imaging technique proposed for the pre-treatment diagnosis of patients undergoing proton therapy. The two main components of our pCT prototype are a proton tracker and a calorimeter. A proton tracker allows precise tracking of proton trajectories, while a proton calorimeter provides accurate measurement of their energies. For our design, we use a specific monolithic active pixel sensor (MAPS) called ALPIDE as an essential part of both a proton tracker and a proton calorimeter. Our pCT prototype has been tested with the Varian ProBeam Compact Proton Therapy System at King Chulalongkorn Memorial Hospital (KCMH), Bangkok, Thailand. The integrated trigger system was also developed to synchronize between the proton beam and the pCT components. The trigger signals are transmitted to activate the rotational stage, produce detection events for the ALPIDE chips, and regulate the proton gating. With this setup, we have studied the possibility of reconstructing proton tracks from activated pixels in a two-sigma region of a Gaussian profile. This study focused primarily on the proton beam, which had the lowest energy of 70 MeV, and the transmission beam used for pCT imaging, which carried an energy of 200 MeV. For both energies, almost 70% of the tracks could be effectively reconstructed from every layer of the ALPIDE chips. The testing results of the pCT prototype run under our trigger system confirm that the ALPIDE chips can be used as integral components for both a tracker and a proton calorimeter.
Speaker: Arnon Songmoolnak (Suranaree University of Technology) -
10:20
Coffee Break
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97
Mini Orals Session III
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98
Enhancing Real-time Data Monitoring Display through Video Streaming Technology
Effective control of experiment flow and real-time monitoring are vital to the growing bandwidth and complexity of data acquisition systems. Unfortunately, platforms like EPICS and LabVIEW are inadequate for handling high data rates. To address this, we create a system that connects a high-speed processing component with a visualization component through a video streaming interface. We further complement the system by introducing our Bora system as the online monitoring that is platform agnostic (integrates with diverse platforms) and remotely available on the web and on mobile platforms. An evaluation of video streaming technologies, such as HLS, MPEG-Websocket, and WebRTC, is presented, assessing their suitability for modern web applications while maintaining real-time display requirements. The method involves comprehensive latency measurements across these technologies, focusing on start-up delay, inter-frame delay, and data transmission delay. Results show varying degrees of efficiency, underscoring the trade-offs between latency, compatibility, and quality. The findings show that, while no single technology is universally superior, HLS and MPEG-Websocket strike a balance between latency and compatibility for general use, whereas WebRTC excels in real-time communication at the expense of increased complexity. This research contributes to the field by providing insights into selecting suitable video streaming technologies for web-based data display. It underscores the importance of balancing data size reduction with system latency and standard interface flexibility to meet the diverse requirements of web applications.
Speaker: Nicholas Tan Jerome -
99
FPGA Tracking with oneAPI
The next era of LHC experiments will provide an unprecedented volume of data, aiming to achieve a tenfold increase in integrated luminosity. Processing these data presents formidable computing challenges. In the case of the LHCb detector, a fully software based trigger has been employed in its current design, which processes events at ~30MHz. Currently, GPU-based compute acceleration is harnessed to manage the high track densities within the detector. The computing challenge intensifies with HL-LHC hit multiplicities, leading to extremely large combinatorics in forming particle tracks from hits. To tackle this challenge, a novel tracking algorithm, employing machine learning, has been devised to generate track stubs for early particle track reconstruction. This algorithm is tailored for deployment on an FPGA, leveraging parallel streams of pipelined neural nets to optimize bandwidth and resource utilization. Central to this approach is the integration of Intel's oneAPI framework. OneAPI enables algorithm development through high-level C++ coding whilst allowing integration with conventional RTL designs. Early profiling tools identify resource estimates and bottlenecks in minutes rather than the hours typical of traditional FPGA development cycles. The machine learning algorithm and oneAPI development cycle will be presented, sharing some early performance measurements using LHCb Vertex Locator data.
Speaker: Karol Hennessy (University of Liverpool (GB)) -
100
Studies on track finding algorithms based on machine learning with GPU and FPGA
Track finding in high-density environments is a key challenge for experiments at modern accelerators. In this presentation we describe the performance obtained running machine learning models studied for the ATLAS Muon High Level Trigger. These models are designed for hit position reconstruction and track pattern recognition with a tracking detector, on a commercially available Xilinx FPGA: Alveo U50, Alveo U250, and Versal VCK5000. We compare the inference times obtained on a CPU, on a GPU and on the FPGA cards. These tests are done using TensorFlow libraries as well as the TensorRT framework, and software frameworks for AI-based applications acceleration. The inference times obtained are compared to the needs of present and future experiments at LHC.
Speaker: Francesco Armando Di Bello (INFN e Universita Genova (IT))
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94
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12:35
Lunch
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13:20
Excursion
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Oral presentations and mini Oral
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101
Development and test of a 48-optical ports high precision clock distributor board
High precision clock distribution is of primary importance for the accurate synchronization of distributed detectors in medium to large-scale physics experiments and in some other scientific instruments as well. Common techniques for distributing a reference clock to a large number of end-points often rely on high-speed serial transceivers embedded in Field Programmable Gate Arrays and use precision phase measurements methods to track, and eventually compensate, distribution delay variations. White Rabbit is a well-known solution that combines these techniques with Ethernet technology. This work explores an alternative approach to clock distribution, specifically in view of the Hyper Kamiokande experiment. We report the design and test of a cascadable 48-optical port clock distributor in 1U x 19’’ standard form-factor. The central element is a commercial System on Module equipped with a Xilinx Zynq UltraScale+ device. Superior port density compared to other designs is reached by using the large available number of ordinary differential I/O pairs instead of the limited count of high speed SerDes. This approach comes at the expense of lower link bandwidth. We detail the concepts and the difficulties of designing fixed-latency high-speed serial communication using ordinary FPGA I/O’s and we investigate interoperability with dedicated multi-gigabit FPGA SerDes. We explain how to implement precise clock round-trip latency measurements with the proposed links. We present characterization measurements obtained with this demonstrator and show its main figures of performance. Finally, we outline how these studies will serve to construct Hyper Kamiokande's final clock distribution system.
Speaker: Denis Calvet (Université Paris-Saclay, CEA, Irfu, France) -
102
JUNO DAQ Design and Status
The Jiangmen Underground Neutrino Observatory (JUNO) is a multi-purpose underground neutrino experiment currently under construction in southern China. JUNO is equipped with 17612 large 20-inch photomultipliers (LPMTs) in the Central Detector, which is designed to detect photons using a high-speed, high-resolution waveform digitization technique. To augment the detection capabilities, 25600 small 3-inch PMTs (SPMTs) are strategically placed in the gaps of the LPMT array. Additionally, 2400 LPMTs are utilized in a surrounding Water Cherenkov detector whose main goal is to identify cosmic ray muons and reduce associated backgrounds. The JUNO Data Acquisition (DAQ) system is designed to manage the massive influx of raw data, which is about 40 GB/s from all the sub-detectors. The JUNO DAQ system is accountable for processing data streams in real-time, including performing online data assembly and event classification, ultimately reducing the data throughput to less than 100 Mbps. This presentation will outline the architectural design and technical implementation of the JUNO DAQ system, along with updates on the ongoing software development and hardware deployment.
Speaker: Xiaolu Ji -
103
Commissioning and Early Experience of the New Online Storage and Express-Reconstruction System for the Belle II Experiment
The Belle II experiment is an experiment at the SuperKEKB, an electron-positron collider, and the Belle II detector operated at the near the energies of Upsilon 4S resonance. The run 1 operation was successfully finished in June 2022, and the first long shutdown was started. During the shutdown period, the online storage and express-reconstruction system has been upgraded. The goals of upgrades are introducing the ZeroMQ library-based framework to the systems like the high-level trigger, direct ROOT format output with online compression, and dedicated express-reconstruction system for physics events tagged by the high-level trigger. In this presentation, we present the commissioning results of the system upgrades and experience of early operation of run 2.
Speaker: Seokhee Park -
104
An Intermediate Level Supernova Pointing Trigger for DUNE Using In-storage AI
One of the main goals of the Deep Underground Neutrino experiment (DUNE) is to detect and study neutrinos from galactic core-collapse supernovas (SNs). In the baseline design, a SN trigger is generated upon detecting sufficient detector activity consistent with a SN candidate. This causes roughly 0.5PB of raw data to be buffered in the underground caverns, as they await network transfer back to Fermilab, lasting several hours. During this time, no attempt is made to determine the direction of the SN. In this talk, we present a new approach that uses in-storage AI implemented on FPGAs to process and reduce the buffered SN data in situ, followed by a fast offline-like workflow that determines the direction of the SN on a timescale useful for optical follow-ups. Apart from making this fast pointing capability possible for the first time, it will greatly impact DUNE's offline data storage requirements in a positive way.
Speaker: Michael H L Wang -
105
Cross-Chip Partial Reconfiguration for the Initialisation of Heterogeneous Systems
Reconfigurability is one of the main advantages of FPGAs over ASICs. Partial reconfiguration exploits this ability even further by allowing to exchange the logic on predefined FPGA regions at runtime. This is especially relevant in heterogeneous SoCs, combining FPGA fabric with conventional processors on a single die. Tight integration and supporting frameworks, such as the FPGA subsystem in Linux, create appealing options, including dynamically loading custom hardware accelerators or real-time logic modules.
Due to the high flexibility and performance of heterogeneous SoCs from AMD Xilinx, they are commonly used in data acquisition systems of all kinds. Qubit control systems based on a single RFSoC are currently limited by the number of readout and manipulation channels and are thus mainly used for characterising a small number of qubits. To scale to hundreds or even thousands of qubits, connecting auxiliary FPGAs to control further channels is a promising option. While cross-chip buses like AXI Chip2Chip allow to easily connect the logic in the devices, partial reconfiguration on the peripheral FPGAs is not supported by the vendor. To overcome this restriction, this contribution proposes a system architecture that uses an AXI Chip2Chip connection in combination with an AXI ICAP controller and custom Linux drivers. This enables the operating system running on the SoC to directly access the configuration ports of the peripheral FPGAs. As a result, updates from the network can be installed at runtime and peripheral FPGA devices can be added and remove during operation.
Speaker: Marvin Fuchs (KIT - Karlsruhe Institute of Technology (DE)) -
10:40
Coffee Break
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106
Mini Orals Session IV
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101
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Poster B
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107
Design and tuning of a fast beam energy selection control system for CYCIAE-230 cyclotron beamline
The preliminary beam test of the CYCIAE-230 cyclotron and its beam transportation system to the isocenter of the gantry was successfully conducted at the end of December 2023. During this, various beam transportation tests with different energies are carried out to verify the design of the energy selection system. The ESS consists of a pair of carbon wedge shape degraders, an apochromatic magnet system, and a related beam shape, the moment selecting slits. Once a beam energy is selected, the rest of the beam transportation system is controlled to follow the ESS, including synchronization of the 51 beamline magnets in total. The CYCIAE230 superconducting cyclotron extracts a fixed energy beam of 242.25MeV. The double wedge degrader and the beamline system are capable of modulating and transporting the beam with energy in a range of 242.25 MeV to 71.84 MeV. In energy range from 232.12 MeV to 71.84 MeV, it experimentally verified to be capable of switching down an energy layer (2mm water depth equivalent) within 50 milliseconds. Different from other degrader designs, the CIAE degrader has a large moment of Inertia, which makes it difficult to achieve fast control. A dedicated energy selection control system has been developed by CIAE, using the VxWorks real-time operating system and its multi-task scheduling to achieve fast control of the degrader and synchronization of the related magnets. To facilitate the commissioning of the beamline, an interpolation algorithm is also included in the reported control system, to automatically calculate the setpoints for different beam energy.
Speaker: Qiqi Song -
108
Online parameter identification and control in the commissioning of nozzle for CIAE
A dedicated pencil beam scan system is developed and integrated into the proton therapy system of China Institute by a joint effort of Pyramid Consult Inc. and China Institute of Atomic Energy. In nozzle commissioning, a proton beam with an intensity of tens nA is provided by the CIAE beam production system, including a 242MeV superconducting cyclotron and a fast energy variable beam transportation system. Most of the scanning devices are commercial products from the pyramid, including the ion chambers, the helium beam path, the magnet, and its amplifier. A Scintillator - camera system named Lynx from IBA, is used to provide position readouts of the beam spot in the commissioning. A dedicated controlling software and related strategy for the beam commission of the scanning system is developed by the CIAE team. In the commissioning, firstly, a straightforward irradiation consisting of 114 beam spots is carried out to evaluate both the nonlinearity and cross-talks of the scanning magnets. Afterward, these coordinates are generated by Lynx and analyzed by the reported software. A modified 2D polynomial fitting, including Hyperbolic Functions, is invested in the commissioning to yield an open loop control accuracy in orders of millimeters. An iterative learning algorithm is also developed to give an even better accuracy. A 50mm separation irradiation map consisting of 37 points is carried out by combining these two corrections on the first day of commission, reaching an accuracy of 0.55mm. An irradiation field of 250mmX250mm is also verified at the same time.
Speaker: Xiong Rui -
109
A 10-Gb/s Serial Link Transmitter With 4-Tap FFE Function in 55-nm CMOS
Due to various wireline transmission scenarios in different detector front-end readout environments, the high-speed chip-to-chip or board-to-board serial data transmission is encountering severe and various signal quality degredations. A general-purpose and high-speed transmitter (Tx) technique with tunable pre-emphasis function is crucial and in great demand. This paper presents the design and test results of a 10 Gb/s high-speed serial link transmitter with the adjustable 4-tap feedforward (FFE) function fabricated in a 55 nm CMOS technology.
The proposed FFE transmitter consists of a demultiplexer (DMUX), two latch-chains, four high-speed MUXes and an output combiner. With this half-rate topology, the needed maximum clock rate is 5 GHz, and thus the full CMOS logic cells can be safely used in the whole design to save power consumption. Besides, a custom-designed high-speed TSPC latch is designed to gain better performance in 5 Gb/s data rate. A high-speed CML-based 2:1 MUX is proposed to achieve the highest data combination in the system. The clock distribution tree is also deliberately designed between each sub-module to ensure suffice timing margins for latches, DMUX and MUXes over different PVT combinations.
The proposed 10 Gb/s 4-tap FFE transmitter features an area of 120 μm×290 μm, and the power consumption is around 50 mW including the CML output driver when working at the date rate of 10 Gbps. The chip has been designed and taped out, and will be tested in September 2023. The test results will be presented and discussed in the meeting.Speaker: Qunqi Shi -
110
A 2.56 Gbps 1:16 Deserializer with a full-rate Clock and Data Recovery for High-Energy Physics Experiments
This paper presents the design and test results of a 2.56Gbps deserializer with a full-rate clock and data recovery (CDR) fabricated in a 55nm CMOS process for applications in high-energy physics experiments.The PLL-based CDR recovers the 2.56GHz clock from the input data and retiming the data.Then the 2.56Gbps retimed data and the 2.56GHz recovered clock are used as the input for the deserializer.The 1:16 deserializer mainly includes a 1:4DEMUX module and a 4:16DEMUX module consisting of 1:4DEMUX units and two divider-by-4, which completes the conversion from a 2.56Gbps serial data to 16 channels 160 Mbps/Ch parallel data.The 1:4DEMUX unit in deserializer is implemented by orthogonal clock sampling, which reduces the requirement of clock frequency and increases the sampling margin.And the LC-VCO in CDR uses a capacitor array with high Q value to realize frequency fine tuning and optimize phase noise.The 2.56Gbps deserializer and the full-rate CDR are integrated in a large chip that has been taped out and fully tested. The test results show that the RMS jitter of the 2.56GHz recovered clock from CDR is 859.71fs with a phase noise of -110dB@1MHz. The total jitter (TJ) of the retimed 2.56Gbps data, which is output from the chip by a CML driver for test, is 32.54ps. And all the 16-channel outputs of the deserializer have been captured, saved and analyzed. Wide-open eyes have been captured, and the logic of 16-channel outputs of the deserializer has been verified. The detailed design and the test results will be presented in the paper.
Speakers: Prof. Di Guo (Central China Normal University), Qiangjun Chen -
111
A 25 Gbps VCSEL Driving ASIC for Detector Front-end Readout
This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology for detector front-end readout. This VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. The input equalizer stage adopts a 5-step CTLE structure to compensate the high frequency loss at the PCB traces, bonding wires and input pads. It can boost maximum up to 5.8 dB at 18 GHz while providing a DC gain of 10.7 dB. To meet both the gain/bandwidth requirements and the area restriction, the pre-driver stage adopts the inductor-shared peaking technology and the active feedback structure. The total gain and the overall bandwidth of the pre-driver stage are better than 18 dB and 19.5 GHz at all process corners, respectively. The proposed output driver stage uses the double feedforward capacitor compensation, T-coil technique and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driving ASIC has been integrated in a customized optical module with a VCSEL array. Both the electrical function and the optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 21.7 ps and the RMS jitter is 3.3 ps.
Speakers: Cong Zhao, Prof. Di Guo (Central China Normal University) -
112
A 4×6.25-Gbs Serial Link Transmitter Core in 0.18-μm CMOS for high-speed front-end ASICs
In this paper, a 4×6.25 Gbps serial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18 um CMOS technology. The core consists of a common PLL and four individual transmitter channels. Each channel contains a 2-stage 20:2 serializer, a 2-stage half-rate feed-forward equalizer and a clock manager circuit. A new architecture of the clock and data path is proposed, and the overall power consumption is reduced by 40% compared with previous works. At a data rate of 6.25 Gbps, the simulation results show that the PLL and transmitter feature a phase jitter of 1.3 ps RMS and 11.2 ps pk-pk respectively. The 4-channel transmitter core occupies 0.44 mm2 and dissipates 27.7 mW/Gbps from 1.8 V supply. The chip is being packaged and will be tested soon in December.
Speaker: Jiacheng Guo (University of Science and Technology of China (CN)) -
113
A Compact Readout Electronics based on Current Amplifier for Micromegas Detector
Abstract—A Compact front-end electronics (Compact_FEC) for reading Micromegas detector is presented in this paper. It includes the detector signal readout module, data acquisition module, and power supply module. The detector signal readout module uses a current-based readout chip, ADAS1128, which integrates 128 current amplifiers for multi-channel charge information measurement. After noise test and calibration, this readout electronics was applied to readout the Micromegas detectors. X-ray with iron-55 source and cosmic ray muon tracking tests were performed to test the energy-resolved and position-resolved performance. 5.9keV X-ray test results show that the Micromegas detector has the full peak charge of 391.3 fc at 5.9 KeV-X-rays, with an energy resolution of 19.50%(FWHM). The Ar escape peak charge of 183.7 fc, with the total peak charge to escape peak ratio of 2.13:1. 5.9keV X-ray measurements are in accordance with the theoretical values. The muon tracking test results for the detector X-dimension spatial resolution of 0.240 mm, Y-dimension spatial resolution of 0.243 mm. The results of the test show that the readout electronics can measure the track of the cosmic ray muon. In summary, the front-end electronics (Compact_FEC), in single-particle measurement mode, can measure signals from the Micromegas detector.
Index Terms — Current amplifiers, Micromegas detector, Readout electronicsSpeaker: Ting Wang (University of Science and Technology of China) -
114
A digital LLRF system based on phase tracking for HALF linear accelerator system
The Hefei Advanced Light Facility (HALF) is the fourth-generation synchrotron radiation light source under construction. The linear accelerator system in HALF will accelerate the beam to 2.2GeV to reach the required luminosity, and a low-level radio frequency (LLRF) system should be adopted to achieve a high-phase-stability RF field inside the accelerator cavities. The phase stability required for the LLRF system is better than 0.02°RMS, which is necessary to achieve high precision phase measurement inside the LLRF system. In this paper, we introduce a phase-tracking-based digital LLRF system designed for the HALF linear accelerator system. The front-end module in this LLRF system is based on high-precision phase discriminator (PD) to obtain DC signal containing the phase information of input sinusoidal waveform. Besides, a differential amplifier and a digital-to-analog converter (DAC) is applied for tracking and amplifying of the phase changes, which is in order to match the input amplitude range of the backend analog-to-digital converter (ADC), and to increase the effective number of bits (ENOB) as much as possible. A Field Programmable Gate Array (FPGA) is adopted to calculate and extract phase information and control the phase-tracking DAC. At the end, we present the test results of the LLRF system and conduct further evaluation based on actual application scenarios in the HALF linear accelerator system.
Speaker: Zhenyan Li -
115
A fast front-end readout design for NICA-MPD shashlik electromagnetic calorimeter
Silicon photomultipliers (SiPMs) are widely recognized for their exceptional light response and high gain characteristics. Nonetheless, their practicality in fast timing applications is often impeded by their substantial terminal capacitance, which commonly exceeds 300 pF. To address this challenge, this study introduces a novel front-end readout electronics design. This architecture comprises a two-stage common-base transimpedance preamplifier and a 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analog-to-digital-converter (ADC). Through extensive SPICE simulations, utilizing the Hamamatsu S13360-6025 as the input source, the preamplifier circuit achieves a rise time of 700 ps and exhibits exceptional linearity. Meanwhile, experimental results from laser testing showcase that the proposed fast preamplifier design achieves a remarkable single-channel time resolution performance of better than 20 ps. As for the ADC circuit, considering the TSMC65nmLP process capability, a two-stage pipelined SAR structure is adopted, incorporating a two-step conversion technique (6-bit + 7-bit), with the second step employing redundancy design to reduce Vref buffer requirements. Experimental testing conducted at a sampling rate of 160M and an input condition of 80M reveals that, for Vpk = -1dBFS, the FFT spectrum analysis of the ADC demonstrates an effective number of bits (ENOB) of 9.34 and a spurious-free dynamic range (SFDR) of 73.8 dBc. Ongoing experiments are being systematically conducted, involving the connection of the fast preamplifier with the ADC, while future research endeavors encompass comprehensive investigations incorporating detectors to evaluate timing resolution in a holistic manner.
Speaker: Mr Xinchi Ran (Tsinghua University) -
116
A Frequency Division Multiplexing Room-temperature Electronics Readout Scheme for TES Calorimeter Arrays
With the progress of material science and thin film preparation technology, the Transition-Edge Sensor (TES) detector-related technologies have been rapidly developed. The TES detector arrays find extensive applications in high-energy physics and nuclear radiation detection. The Frequency Division Multiplexing (FDM) technology is one of the mainstream multiplexing technologies used in TES readout that reduces thermal load. This paper presents the principle of the TES for applications in astrophysics and particle physics. Then, it proposes a room-temperature electronics readout scheme for the FDM readout system of the TES arrays. This scheme enables precise adjustment of the 40-channel TES bias signals so that the TES arrays can operate at the set optimal operating frequency. This scheme achieves high-precision amplification, sampling, processing, and feedback of TES signals. In the feedback algorithm, the logic resources of FPGA are used to achieve accurate phase compensation.
Speaker: Jianguo Liu (University of Science and Technology of China (CN)) -
117
A Fully Reconfigurable Pipelined Architecture for FPGA-based Parallel PRBS Test Pattern Generators
Serial links are widely used for data transfer in Data Acquisition (DAQ) Systems of High Energy Physics (HEP) experiments. Pseudo-Random Binary Sequences (PRBS) has seen wide application in high-speed serial wireline communication systems as test patterns for link characterization and testing. A flexible architecture for FPGA-based PRBS generators is proposed, with a focus on high throughput and full reconfigurability. In order to meet the demands of increasing data rates, the proposed architecture employs a parallel datapath with high scalability. The architecture is designed to be fully parametric and reconfigurable, which allows dynamic reconfiguration of all parameters of the PRBS generator on the fly, including polynomial, seed and output width. Reconfiguration of the parameters is achieved by simply writing to corresponding registers, without the need to re-synthesize or re-configure the FPGA device. A built-in bootstrap logic is used to convert parameter register values to internal states that are fed to the datapath to generate the output bit sequence. The datapath is pipelined to facilitate optimized timing performance on FPGA devices. The proposed design can be utilized to characterize serial link performance under a great variety of different test patterns rather than several selected ones, providing broader insights. The architecture is implemented in CHISEL and verified on an Intel Agilex-7 FPGA and a 106.25-Gbps serial link, where results show promising performance and scalability.
Speaker: Chengyang Zhu (University of Science and Technology of China) -
118
A high-precision two-stage Time-to-Digital Convertor in 180 nm CMOS Technology
In the field of particle physics experiments, Time-of-Flight (ToF) is a powerful tool to perform particle identification, and the Time-to-Digital Converter (TDC) plays a crucial role in the high-precision time measurement. As the momentum of the particles to be studied increasingly goes high, the time resolution requirement becomes higher accordingly, and the TDC is expected to achieve picosecond (ps) time precision. Moreover, high-resolution measurements are also widely demanded in other scientific domains, such as LIDAR, TOF-PET, etc. In this work, the design and testing of a 16-channel coarse-fine hierarchical TDC is present. It utilizes a two-level conversion structure combined with a coarse counter to achieve a wide dynamic range with high time resolution. The coarse time is measured with a shared two-edge counting gray counter, and the fine time is obtained with a dedicated two-stage TDC, which is composed of a delay line TDC and a Vernier TDC. The bin size of TDC is approximate 7 ps. To implement a low-jitter clock generation circuit with a small area, a multiplying delay-locked loop was employed, and with a fixed patter noise calibration, the clock jitter was achieved better than 3 ps. The ASIC was implemented in a standard cost-effective 180 nm CMOS process, and test results show that the TDC reaches a dynamic range of 5 μs with 8.5 ps precision for all channels, while utilizing less than 10 mW/chn.
Speaker: Jiajun Qin (University of Science and Technology of China (CN)) -
119
A lock-in amplifier module for CO2 dispersion interferometer on EAST tokamak
To measure plasma density and provide real-time feedback for the control system, we have established a carbon dioxide dispersion interferometer (CO2-DI) system on the EAST tokamak device. Due to the low efficiency of the frequency-doubling crystal, the power of the second harmonic is extremely low. To obtain accurate interference information, it is necessary to use a lock-in amplifier to acquire modulation signals at 50k and 100k and process the intensity of this signal to obtain plasma density.
In our design, a lock-in amplifier module consists of two main components, the lock-in amplifier and the real-time data acquisition system. A dual-phase lock-in amplifier is designed. By two phase channels, the dual-phase lock-in amplifier can better handle complex signals and provide more comprehensive phase information. This capability makes it suitable for extraction of weak signals in CO2-DI. The real-time data processing system is implemented on a development board, utilizing Xilinx FPGA for digital signal processing and interfacing with the backend for output. The module is applied in CO2-DI to extract small signals and perform real-time data processing. We cross-validated the processed density data with results obtained from two other interferometers. The results indicate that the entire system has successfully obtained valid and verifiable electron density data.Speaker: Yuan Yao (ASIPP, Chinese Academy Society) -
120
A low-complexity MLSE algorithm for the NRZ high-speed transceivers
In this article, a low-complexity maximum likelihood sequence equalizer (MLSE) algorithm for non-return-to-zero (NRZ) high-speed transceivers is proposed. In particle physics experiments and high-energy physics experiments, the amount of data transmission continues to increase, and transceivers play an important role. MLSE has received widespread attention because of its great advantages in eliminating inter-symbol interference (ISI), and it can work instead of a decision feedback equalizer (DFE). However, the complexity of MLSE also increases exponentially with the traceback length and equalizer order. Therefore, it is important to reduce the complexity of MLSE while ensuring its performance. This article simplifies the calculation of transition metrics for MLSE, eliminating the need for complex state calculations and result storage. A configurable and highly flexible transceiver simulation system is designed based on a field programmable gate array (FPGA), and the proposed algorithm is tested with this system. Quartus software synthesis results show that the proposed algorithm significantly reduces resource consumption without loss of algorithm performance.
Speaker: Dongwei Zou (University of Science and Technology of China) -
121
A pixel matrix prototype chip with high-precision time measurement for CMOS pixel detectors
CMOS pixel detectors, characterized by high spatial resolution, high sensitivity, and low material budget, are ideal for tracking charged particles. As a result, they have been widely used in particle physics experiments, and are considered the preferred technology for future vertex detectors. Particle physics experiments are constantly moving toward higher luminosities, placing greater demands on future detector performance. The integration of high-precision time measurement functions in CMOS pixel detectors allows the simultaneous measurement of particle hit positions and time of arrival (TOA). This so-called 4-D (four-dimensional) tracking capability allows for event discrimination on the time scale, reducing event pile-up and improving particle track reconstruction. To investigate the feasibility of integrating high-precision time measurement capabilities into CMOS pixel detectors, a pixel matrix prototype chip has been designed, based on a CIS 180 nm process. Each pixel in the pixel matrix is composed of a charge collection diode, a front-end charge signal processing circuit optimized for high timing accuracy, and a common time quantization circuit shared by 8 pixels. In response to the demand for low power consumption and high reliability in the pixel circuits, a time quantization method has been employed that combines fine time stamp measurements within the pixel and coarse time stamp measurements at the periphery of the pixel matrix. This method, along with a fully synchronous zero-suppression readout approach, achieves a time digitization of TOA with a bin size of 2 ns.
Speaker: Mr Boyu Cheng (University of Science and Technology of China) -
122
A radiation trace recognition framework for the Timepix event data
Timepix is a semiconductor single-particle-counting pixel detector developed by the Medipix2 Collaboration at CERN. Timepix can create images of the traces of recored particles. Each arriving particle leaves a separate trail on the detector due to the charge sharing effect. The radiation trace on a image provides useful information for identifying the recorded paticles as well as their paths. The aim of this study is to propose a cluster classification algorithm for separating and analyzing each cluster inside an image. First, the clusters are extracted separately using the algorithm based on the definition of a cluster: a group of adjacent pixels that is independent of other clusters. Next, cluster's morphology parameters (number of inner/border pixels, width, height, cluster area radius, maximum distance in clusters, and so on) are examined. Finally, all clusters were divided into the following groups based on their geometrical features: dot, small blob, curly track, heavy blob, heavy track, and straight track. This study presents a quick and efficient framework for analyzing Timepix silicon detector data.
Speaker: Mr Trình Nguyễn Ngọc Quốc -
123
Advances in Readout Electronics for STCF ECAL
Super Tau-Charm Facility (STCF) is one of the important options for accelerator-based particle physics in China. The operation of the STCF will provide a unique platform for the study of tau-charm physics and hadron physics.
Electromagnetic Calorimeter (ECAL) is one of the important sub-detectors of STCF, and Its core task is the precise measurement of photons. In the face of complex background environment, STCF ECAL needs to obtain accurate energy information and time information of photons at the same time to effectively suppress the background, so compared with traditional electromagnetic energy generators, STCF ECAL puts forward higher requirements for temporal resolution.
STCF ECAL selects pure Csium iodide (pCsI) as its scintillation crystal, and uses a large-area avalanche photodiode (APD) to make up for the shortcomings of low pCsI optical yield.
In order to meet the above readout electronics requirements, this paper determines the energy measurement scheme based on the Charge Sensitive Amplifier (CSA), and uses algorithm to deal with the pile-up signal, and the energy information and time information that meet the measurement requirements of STCF ECAL can be obtained.
In order to meet the needs of high-precision energy and time measurement in the environment of high case rate of STCF ECAL, the readout electronics scheme was studied and designed, and the feasibility of the scheme was verified by combining with the prototype electronics system, which provided a technical basis for the future development of STCF ECAL.Speaker: Hanlin YU (University of Science and Technology of China) -
124
AI-Based Online Spectral Classification of Copper Alloys using Prompt-Gamma Neutron Activation Analysis (PGNAA)
Due to environmental, economic sustainability, and political considerations, recycling processes are gaining heightened significance, focusing on substantially increasing the utilization of secondary raw materials. This paper advances the field by tackling the novel challenge of non-destructively analyzing mixed copper alloys. Building on our previous work in non-destructive analysis of different materials and metal alloys, this paper addresses the novel challenge of analyzing mixed metal alloys, which include similar alloys. The increased similarity among these mixtures poses a greater challenge and enhances their relevance.
In the recycling of copper alloys, online classification is not only concerned with categorizing individual alloys but also with identifying mixtures of these alloys and determining their composition ratios. We employ a non-destructive material analysis based on PGNAA using a High Purity Germanium (HPGe) detector. In our AI application, we utilize three classification methods, such as Maximum Log Likelihood, Neural Network (NN) and Convolutional Neural Network (CNN), to overcome this challenge. Furthermore, we demonstrate a significantly better performance in CNN classification of copper alloys compared to the current state-of-the-art, achieving a higher classification rate in only one-fifth of the time.
We evaluate the classification accuracy of each method and achieve nearly perfect results with less than one second of classification time. This demonstrates the possibility of online classification between mixed materials with even similar alloys.Speakers: Helmand Shayan, Dr Markus Lange-Hegermann -
125
Alarm and recovery system in the Belle II operation
The Belle II experiment seeks physics beyond the standard model of particle physics exploiting the data provided from the SuperKEKB accelerator.
To maximise the sensitivity to physics beyond the standard model, we collect as much data as possible.
Minimising the time without data-taking is a key to collect more data.
We have started our physics data-taking on March 2019, maintained the good data-taking efficiency since then.
Nevertheless, we encountered various problems and errors during our operation.
During the first running period (2019-2022), we established a system which automatically diagnose and fix known errors with no human interaction, hence we minimise the time without data-taking.
In the shutdown period (2022-2023), we implement a number of new alarms to monitor the detector environment, the data quality, and the data-acquisition system, thereby, we ensure the detector safety and the data quality in the next running period (2024-2027).
In the case of severe errors, it is expected that we encounter multiple alarms at the same time during the next running period.
In order to categorise the alarms activated simultaneously, we adopt the alarm system based on Control System Studio (Phoebus).
In this contribution, we present the current status of the system together with the difficulties experienced during the operation.Speaker: Takuto Kunigo (KEK (IPNS)) -
126
An FPGA-based ADC for PET module applications
Positron emission tomography (PET) is an advanced clinical examination imaging technology in the field of nuclear medicine. We will describe a novel PET module using a soft-core analog-to-digital converter (ADC) based on time-to-digital converter (TDC). The soft-core ADC is implemented in an FPGA. In the hardware design, the FPGA-based ADC (FPGA-ADC) only requires one resistor and an FPGA. FPGA-ADC allows users to program the sampling rate and adjust the dynamic range of the ADC with small modifications. This design is characterized by flexibility and high density, which can greatly reduce the size of readout circuits for the PET module.
In this PET module, detector will use a 15×15 (the size of crystal bar: 1.535 mm ×1.535mm ×20 mm) LYSO crystal array coupled with an 8×8 SiPM (J-series, from ON Semiconductor) array. The FPGA-ADC serves as the main part of the data acquisition (DAQ) system. For coincidence timing measurement, one reference detector is used in our experiment and to remove the background noise of LYSO crystal. It is possible for the FPGA-ADC to perform full waveform sampling on the raw signal of PET module. Good position and energy resolution can be achieved using the FPGA-ADC for the PET module.Speaker: songqing liu -
127
Anovel readout scheme and low-power design for silicon pixel chip applications
The Low Energy X-ray Polarization Detector (LPD) is one of the three payloads of the Gamma-ray Burst (GRB) Polarization Detector Space Station Detection Facility.LPD payload contains technologies such as the silicon pixel detector chip, the GMCP and high-power power supply. Pixel chip needs to be characterized by high effective detection area, high spatial resolution and low power consumption, which poses new challenges to performance requirements of the readout module of the chip.
This paper designs a pixel chip Topmetal-L with a novel readout scheme,the readout mode of the chip adopts the Region of interest (ROI) readout,it realizes fast readout for pixel units with particle injection. The ROI readout module is embedded in an L-shaped pattern around the pixel array, and module quickly reads out effective pixels by confirming the start pixel, the cutoff pixel, and number of pixels jump during scanning.The electronic system collects and processes the output signals of the pixel units, determines the areas where there is particle injection, and feeds back to the module to quickly scan to that pixel area and read it out. The module can control the driving circuit of each pixel, reducing chip power consumption.
The simulation results show that ROI readout effectively improves the readout rate of the chip and can meet the readout requirements under the strongest GRB conditions. The module can achieve fast readout with only one channel, significantly reducing the electronic power consumption of the payload. The introduction of drive switch effectively reduces the power consumption of the chip.Speaker: Mr 强 周 (华中师范大学) -
128
CMOS MAPS with a novel readout scheme for the STCF Inner tracker
The super tau-charm facility(STCF) is a proposed e+e- collider producing a data sample 100 times higher than present tau-charm factory (BEPCII). The inner tracker of STCF should have certain position resolution, time resolution, charge measurement function and low power consumption and one of its alternative options is semiconductor detector based on monolithic active pixel sensor (MAPS). However existing readout structures of MAPS either have high power consumption or cannot readout ToT information correctly. To satisfy these requirements, a novel readout scheme has been developed in a full-custom manner. On the one side, it uses VCO in super pixels to record time-of-arrival (ToA) at 500MHz with extremely low static power consumption. On the other side, outputs of front-end circuits are combined through OR gates with the interval of multiple pixels in both directions, which avoids the loss of time-over-threshold (ToT) caused by OR gates. Finally, a group address is read out simultaneously to prevent degradation of position resolution caused by channels merging. A readout calculation model has been established based on MATLAB and simulation results illustrate the readout efficiency is higher than 99% until hit rate becomes 10 MHz/cm2, which corresponds to more than 10 times average counting rate of STCF ITK. According to simulation, the digital power consumption is lower than 30 mW/cm2 while timing resolution of ToA is 2 ns.
Speaker: Dongwei Xuan (University of Science and Technology of China) -
129
Design and Implementation of Single-server DAQ System for HEPS-BPIX4
X-ray detectors are crucial components for advanced photon sources. IHEP (Institute of High Energy Physics, Chinese Academy of Sciences) has initiated the indigenous development of silicon pixel detectors (HEPS-Beijing Pixel, HEPS-BPIX) over the past decade for High Energy Photon Source (HEPS), and is currently working on the fourth-generation detector (HEPS-BPIX4).Considering the large detection area, high spatial resolution, wide dynamic range, and high frame rate acquisition of the HEPS-BPIX4, a single-server based HEPS-BPIX4 DAQ system, featuring high integration, has been meticulously designed and implemented. This DAQ system is comprehensive in functionality and exceptional in performance, having been jointly tested with single detector module to ensure its reliability and effectiveness.
Keywords: High Energy Photon Source, Silicon Pixel Detector, DAQ
Speaker: Mr Xuanzheng Yang -
130
Design of a 0.8 V Low-voltage High-rate Prototype Readout ASIC for the μRWELL-based Inner Tracker Detector
The peak luminosity of the Super Tau-Charm Facility (STCF) proposed by the Chinese particle physics community is about an order of magnitude greater than the present Tau-Charm factory. In the STCF, the micro-resistive well ($\mu$RWELL) based inner tracker detector, located closest to the beamline, demands a new high-rate, low-noise, and low power Application Specific Integrated Circuit (ASIC). The first version prototype ASIC integrates 32 readout channels, each consisting of a Charge Sensitive Amplifier (CSA), a Pole-Zero Cancellation (PZC), a shaper, and an output buffer. The supply voltage is designed to be 0.8 V to reduce power consumption while maintaining the same channel thermal noise and transconductance, and the core amplifier of the CSA achieves an open-loop gain of 74.2 dB and a Gain-BandWidth product (GBW) of 1.55 GHz with only 900 $\mu$W power consumption. In addition, a fast recovery circuit is designed to reduce the dead time. This ASIC has been taped out in a 0.18 $\mu$m CMOS process and a series of post-layout simulations have been performed. The dead time for a single channel is less than 250 ns, resulting in a maximum counting rate capability of 4 MHz. The equivalent noise charge (ENC) is 698 e + 23 e/pF while the power consumption is about 2.2 mW per channel, resulting in a figure of merit (FOM) of only 0.31 pJ.
Speaker: Mr Jiaming Li (University of Science and Technology of China) -
131
Design of a 11-bit column-parallel ADC for Monolithic Active Pixel Sensor
The Monolithic Active Pixel Sensor (MAPS) has been widely used in nuclear and particle physics. The various physics and applications at the Heavy Ion Research Facility in Lanzhou (HIRFL) and the High-Intensity Heavy-ion Accelerator Facility (HIAF) require MAPS to measure particle hit's position, energy deposition, and arrival time. Thus, a MAPS with such capability has been designed in a 130nm process. As the critical part of the MAPS, an 11-bit column-parallel ADC has been designed to serve the pixels in every two adjacent columns.
The ADC uses cyclic architecture to meet the strict requirements of the area and removes SHA to save power. In addition, a novel MDAC architecture with two residue generators is proposed. By configuring the MDAC in pipeline mode, the MDAC reduces the high power consumption of the high-performance amplifier without increasing area consumption. The core amplifier is optimized in pseudo-differential operation to avoid additional single-ended-to-differential converters.
Each column-parallel ADC covers an area of 60×670 μm2 and consumes a power of 3.33mW with a 3.3V power supply. At an internal clock frequency of 40MHz, the ENOB of the ADC reaches 10.89 bits at a sampling rate of 4MHz, and the SNDR is 67.3dB.
Speaker: Weijia Han (Institute of Modern Physics, Chinese Academy of Sciences) -
132
Design of a 14-bit 40MSPS Pipeline Regional ADC for Monolithic Active Pixel Sensors.
As the leading research platform of heavy-ion science in China, the heavy-ion physics and heavy-ion applications at the Heavy Ion Research Facility in Lanzhou (HIRFL) and the High-Intensity heavy-ion Accelerator Facility (HIAF) drive the development of new detector technology. A Monolithic Active Pixel Sensor (MAPS) has been designed in a 130nm process for HIRLF and HIAF. This MAPS can measure the energy deposition, the hit position, and the arrival time of the particle hit. As the critical component of this MAPS, a 14-bit 40MS/s regional pipeline ADC converts the analog energy and time signal from the pixels into digital data. It adopts the structure of SHA(sample-and-hold)-less and a first stage of 3.5-bit. Additionally, in order to improve the accuracy of conversion, bootstrapped switches, input offset storage technology, and the redundancy algorithm have been used in the design. With a power consumption of 138mW and an area of 1380μm×1300μm, this ADC can achieve the SFDR of 98.60dB, SINAD of 83.36dB, and ENOB of 13.56-bit.
Speaker: Yuan Tian -
133
Design of a Pixel Readout Chip for Silicon Drift Detector With Event Driven Readout Method
Since using X-ray pulsars for autonomous navigation of spacecraft was proposed, it has attracted attention from all parties because of its superior performance. As a commonly used semiconductor detector, the Silicon Drift Detector has high energy resolution, high linearity, and low noise, which are optimized for the detection of X-rays in the range of 0.5 keV to 10 keV.
The readout chip, fabricated in CMOS 130 nm, has 5 mm × 5 mm dimensions. The core of the IC is a matrix of 40×50 pixels with 80 um ×80 um pixel size. When SDD converts the incoming photons of X-ray into charge changes, the readout circuits will receive and convert these slight charges into a voltage proportional to the X-ray photon's energy. The chip uses the event-driven method to output the addresses of the pixels being hit and the corresponding energy signal of the incident X-ray photon and outputs the arrival time of the X-ray photon.
The power consumption is 31uW/pixel at a 1.5V power supply. The following simulation results use the default status of the chip after it is powered on as an example, and the readout electronics are optimized for collecting holes in this state. The charge to voltage gain of CSA is 96.13 μV/e- and the equivalent noise charge is equal to 36 e- rms (@detector self-capacitance Cdet=50fF). The pixel-to-pixel offset spread of the pixel matrix reached σ = 10.6 mV rms, and it was reduced to σ = 1.51 mV rms after correction by trim DAC.Speaker: Mr Wenxuan Cao (Harbin Institute of Technology) -
134
Design of an FPGA-based USB 3.0 controller
The traditional USB 3.0 communication based on FPGA uses an external chip as a USB PHY or a USB controller including a USB PHY. This paper realizes a USB 3.0 controller using FPGA resources, in which FPGA logic realizes a serial interface engine, and an FPGA internal transceiver is a USB PHY. Used slices percent after implementation is ~5% in Kintex-7 325t. The test result shows that the speed of USB 3.0 is more than 320 MB/s bulk-in and bulk-out transfers.
Speaker: Zhe Ning -
135
Design of application of the CDAU, a common data acquisition unit for HIAF
In particle physics and nuclear physics experiments, especially experiments based on particle accelerators, the data transmission rate of the detector is very high. These high throughput data from the front-end electronic of the detector need to be transmitted to the PC for the selection and summary of the event. Data acquisition (DAQ) systems with high density, scalability, and easy upgrading are essential to simplify the reading architecture of the entire experiment. A common data acquisition unit (CDAU) has been designed in a scalable DAQ system for particle physics and nuclear physics experiments at the High Intensity Heavy Ion Accelerator Facility (HIAF). The CDAU is a PCIe-based FPGA data acquisition readout unit. The same unit handles the data acquisition and distributes slow control to the detector's front-end electronics. The CDAU is based on a PCI Express (PCIe) Gen 2 × 8 interface and interfaces to eight optical links via a QSFP transceiver and four SFP+ transceivers for data collection, packaging, and transmission, using a Xilinx Kintex series FPGA as its central chip, combined with optical interfaces and peripheral circuitry. This paper presents the design of the CDAU, its performance, and its application test. As a result, it is proved that the CDAU can perfectly realize data transfer through the transmission link and accomplish data restoration. Thus, the system can meet the needs of HIAF experiments. We are now preparing joint tests with different multi-channel detectors in physics experiments. More experimental results will be presented in the meeting.
Speakers: Chengcheng Liu (Institute of Modern Physics, Chinese Academy of Sciences), Mr Honglin Zhang (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Haibo Yang (Institute of Modern Physics, Chinese Academy of Sciences), Mr Jieyu Zhu (Institute of Modern Physics, Chinese Academy of Sciences), Mr Xianqin Li (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Chengxin Zhao (Institute of Modern Physics, CAS) -
136
Design of Large Dynamic Range Readout Electronics for the Prototype Calorimeter of VLAST
The Very Large Area gamma-ray Space Telescope (VLAST) is a high-energy detection satellite proposed by Chinese scientists aimed at conducting high-energy resolution spatial observations of gamma rays with unprecedented acceptance. As one of its sub-detectors, the High-Energy Imaging Calorimeter (HEIC) is used to measure the energy deposited by incident particles and to identify particles based on the shape differences between electromagnetic showers and hadronic showers. To achieve detection of 0.1 GeV-20 TeV gamma rays and electrons, a prototype calorimeter was proposed, which is composed of four layers, each with 25 BGO (Bismuth Germanate Oxide) crystal. Two identical Avalanche photodiodes (APD) are used for photoelectric conversion of a crystal, one of which is interposed with an attenuating filter. This paper proposes a readout electronics system for the prototype calorimeter. Signals from the APDs are amplified and shaped by CSA (Charge Sensitive Amplifier), then split into high and low electronics gains to achieve a large dynamic range. The analog signals are digitized by ADC (Analog-to-Digital Converter), and the waveform data of each layer is concentrated by Data Concentrator Module (DCM) and sent to computer for processing. The key indexes of energy linearity, noise level, and dynamic range were preliminarily studied. The ratio of the maximum input charge to equivalent noise charge in the readout electronics is about 1.4 × 10$^4$, which meets the large dynamic range requirements of the readout system.
Speaker: Qian Chen (University of Science and Technology of China (CN)) -
137
Design of Nupix-A2, a Monolithic Active Pixel Sensor for Heavy-ion Physics
The High-Intensity heavy-ion Accelerator Facility (HIAF) is under construction to generate intense beams of primary and radioactive ions for various research fields. Among the different detector technologies, the Monolithic Active Pixel Sensor (MAPS) stands out due to its integration of the pixel matrix and readout circuit into a single silicon substrate. Hence, a MAPS named Nupix-A2 has been developed in a 130-nm High Resistivity CMOS process. The Nupix-A2 can simultaneously measure energy, arrival time, and position of the particle hits. What is more, the Nupix-A2 offers two operation modes, the full-readout mode and fast-readout mode, for different applications. It comprises a 128×128 pixel array, a digital-to-analog converter array, and a digital control module. The size of each pixel is 30 μm×30 μm. The Nupix-A2 can measure energy deposition from 300 e- to over 50 ke- and time duration from 13 μs to 140 μs. The S-cure shows the performance of the comparator, while the transfer noise (TN) is approximately 14.3258 e-, and the threshold is ∼300.112 e-. For the energy path, while using the test capacitor to inject charge, a maximum Integral Non-Linearity (INL) of 1.568% was observed within the 0 to 23.58 ke- range. As for the time path, when the range is 40 μs with the charging current at ∼4 nA, the maximum INL value is 2.88%. This paper will discuss the design and preliminary test of the Nupix-A2.
Speaker: Ju Huang (Institute of Modern Physics, Chinese Academy of Sciences) -
138
Design of the data acquisition system for the transition radiation detector prototype
The Transition Radiation Detector (TRD) of the High Energy Cosmic Radiation Detection facility (HERD) utilizes the relationship between high-energy charged particle transition radiation and the Lorentz factor to calibrate the energy of TeV-band protons in HERD calorimeters. It can also independently conduct X-ray observation and monitor Gamma-Ray Bursts . The TRD mainly consists of detector units, front-end electronics, and data acquisition system. The data acquisition system is responsible for the overall power management of the TRD, communication and triggering between the TRD and HERD, data processing of the detector units, control of multiple modules within the TRD, and in-orbit operation of the whole TRD. Here we report a prototype of the TRD data acquisition system, which connects six front-end circuit boards, six high-voltage circuit boards, a turntable device, HERD triggering subsystem, and HERD electronics. It adopts a structure with separate data and electrical components, with the power sections of the front-end electronics, high-voltage, turntable device, and data acquisition system designed as power circuit boards, and the FEE data transmission and telemetry, triggering, main control, storage, and communication designed as data circuit boards. We tested our data acquisition system prototype at the European Organization for Nuclear Research, and the results show that the system can meet the requirements of the TRD prototype in terms of power, communication, data processing, and overall control. We also demonstrate that the data acquisition system has been redundantly designed to enhance adaptability.
Speaker: Hui Wang (Central China Normal University) -
139
Developing an Arduino-Based Peak Detector Circuit for Gamma Spectrum Measurement
In this article, we describe the development of an electronic circuit for measuring the pulse amplitude of scintillation detectors using an Arduino Mega2560pro (Embed). The amplified analog signals are fed into a peak detector circuit (Lew Counts and Mark Murphy, Analog Dialogue 24-2, 1990). In addition to this circuit, we have incorporated components such as opamp comparators, flip-flops, and analog switches to ensure accurate signal sampling through the Arduino. To test the system's performance, we used standard pulses with amplitudes ranging from 200mV to 3200mV generated by the RIGOL DG4062 pulse generator. The survey results show a full-scale non-linearity of less than 0.5%. Furthermore, we measured the energy spectrum of gamma rays emitted by various isotopes such as Ba-133, Na-22, Cs-137, and Co-60 using a NaI(Tl) detector (model 44-10) and counter (model 4612) manufactured by Ludlum Measurements, Inc , and our system. The results indicate that the Full Width at Half Maximum (FWHM%) at 81KeV is 15.46%, at 356KeV is 9.90%, at 511KeV is 8.57%, at 662KeV is 8.36%, at 1173KeV is 5.24%, and at 1332KeV is 6.15%. This is a simple and cost-effective design that can be used to construct gamma-ray spectroscopy devices for educational purposes.
Speaker: Ms Thi Minh Hien Nguyen (Centre For Applications of Nuclear Technique in Industry) -
140
Development and commissioning of the beam diagnostics for CIAE proton therapy beamline system
A superconducting cyclotron based proton therapy system has been developed at China Institute of Atomic Energy (CIAE) for years. The system has technical advantages such as high dose rate, fast energy varying, compact structure, and low energy consumption. From the cyclotron to the nozzle, the beam line employed 51 magnets, including six 30°, one 60°, and two 75° dipoles. It can be seen that its strict symmetry ensures the better beam optics, such as chromatic aberration for the beam with wide energy range. In order to meet the beam commissioning needs of such high-quality beam lines, the beam diagnostics system has been developed in house successfully. Along the beam line, the system includes: 1) 7 standardized comprehensive diagnostic units (a combination of Faraday cup, dual wires scanner, and optical beam profile monitor); 2) 4 pairs of X-Y slits for energy selection and emittance re-definition; 3) several separate circular collimators, fast beam cutoff devices, and online monitoring ionization chambers for beam position, as well as Faraday cup for measuring beam intensity in the air section for flexible use. In this paper, the design of the diagnostic system, the specialized electronics, the EMC consideration will be given. And the dual wire structure for pA level weak beam will be introduced, the Ce doped yttrium aluminum garnet (Ce:YAG), which is an important photonic material that is used as a yellow phosphor for white light emitting diodes, has very low intensity threshold for proton beam profile measurement will also presented in detail.
Speaker: Yang Wang -
141
Development of a High-Bandwidth Waveform Processing System using RFSoC for RI Beam Experiments
We have developed a digital waveform processing system with AMD RFSoC.
It is optimized system for experiments at RIKEN RI Beam Factory(RIBF) that is an accelerator facility in Japan.
This system is aimed at simultaneous measurement of TOF with high-resolution and ΔE using plastic scintillators.
The AMD RFSoC includes 4GHz FADC, FPGA, and CPU, and it is expected that this system that allows pipeline processing of high frequency signals without dead time can be established.
We have successfully developed the algorithm to obtained timing and charge information simultaneously by adopting centroid calculation for the waveform processing method. Especially, a very good timing resolution of 9 ps in sigma was achieved. At present, we are trying to implement this method to RFSoC as an FPGA IP core.
In this contribution, the algorithm for the extraction of timing and charge information from a waveform, and the implementation of FPGA firmware will be reported.Speaker: Shoko Takeshige (Rikkyo University, RIKEN Nishina Center) -
142
Development of warm readout electronics for Time-division Multiplexing SQUID
Superconducting transition-edge sensor (TES), operating in the mK temperature range, exhibit extremely low noise levels and excellent energy resolution. TES is widely used in the detection of cosmic microwave background radiation (CMB) and in synchrotron radiation, free-electron laser spectrometers. As the number of detector increases, the heat loading to the mK stage of refrigerator from the conducting of the read out cable from the mK stage to room-temperature will increase significantly. As the cooling capacity of refrigerator at mK is limited, this will limit the scale of the TES array. To increase the number of the TES detector, the mutiplexing cryogenic readout electronics is involed to readuce the number of the read out cable. The most mature technology is the time-division multiplexing (TDM) superconducting quantum interference device (SQUID). This paper focuses on the development of warm readout electronics for TDM. The two-stage SQUID readout architecture of TDM achieves multiplexed readout of multiple detectors by cyclically selecting each row’s first-stage SQUID, controlled by SQUID superconducting switching. This greatly reduces power consumption at each stage. We use a analog-to-digital converter (ADC) with a sampling rate of up to 125MSPS and 16-bit resolution to receive data. The data is then processed in real-time using a digital proportional-integral-derivative (PID) feedback algorithm in FPGA. We also use a 16-bit, 2.8GSPS digital-to-analog converter (DAC) to send synchronous SQUID magnetic flux locking signals. The goal of this work is to achieve a single-channel 20:1 multiplexing factor and to perform high-speed real-time data processing based on FPGA, GPU.
Speaker: Mr Nan Li (Shandong University) -
143
First performance results for the ZDC Readout Electronics of the external target experiment at HIRFL-CSR
The CSR External-target Experiment (CEE) at the Heavy Ion Research Facility at Lanzhou (HIRFL) will be the first large-scale experiment in nuclear physics independently developed in China, covering the GeV energy regime. As a major detector of CEE, The Zero Degree Calorimeter (ZDC) measures the centrality and reaction plane of the nuclear-nuclear collision from the hadron background. It comprises Plastic Scintillator (PS) crystal bars with a fan-shaped size for each. The PS bars directly coupled with a PMT (photomultiplier tube) to convert charged particles into electrical signals. The readout electronics consists of 12 Frond-End Cards (FECs), 12 Read Control Units (RCUs), one sub-trigger module, one sub-DAQ module, and one sub-clock module. In addition, there is one HV (High Voltage) crate providing a high voltage supply for the PMTs to provide power supply for the nearby PMTs. On the basis of the previous version of the prototype, in order to improve the performance of the detector, achieve a wider measurement range, and better electronic performance. This article introduces the upgrade of detector readout methods, electronic hardware and data processing algorithms, integration with CEE DAQ, trigger, clock and other subsystems, and long-term stable operation in engineering. The test results indicate that the noise performance is less than 1 mV (RMS), the nonlinearity of the full readout electronics is less than 0.7%. In addition, cosmic ray test results demonstrate that the readout electronics can reach good performance.
Speaker: Xianqin Li (Institute of modern physics, Chinese Academy of Sciences) -
144
Front-end Electronics for the Prototype of HERD Transition Radiation Detector
The High Energy Cosmic Radiation Detection Facility (HERD) is a part of the Chinese Cosmic Lighthouse Program in China’s Space Station, which will be launched in 2027. HERD is expected to work ten years in orbit and will indirectly detect dark matter, measure cosmic rays, and observe high-energy gamma rays. As a sub-detector of HERD, the transition radiation detector's (TRD) main scientific goal is to calibrate the electromagnetic Calorimeter (CALO) at the TeV energy range, improve the measurement accuracy of the CALO, and detect astronomical phenomena of high-energy gamma rays. The front-end readout electronic (FEE) of the prototype TRD uses four SAMPA ASICs for 128 anode signals, realizing a high-speed, low-power, and high-reliability data acquisition system. The FEE uses the R422 bus to communicate with back-end electronics for commands, state parameters, environmental parameters, and triggers. Scientific data transmission at 80 Mbps via LVDS protocol. The performance test results show that the dynamic range of the FEE is 0-100 fC, the RMSE of the channel noise is less than 1.7 fC, the linearity can reach 0.2%, and the amplitude resolution is better than 3% when the input charges exceed 20 fC. A beam test was performed at the CERN SPS and PS complex to verify the FEE performance further, and the experimental results show that the FEE meets the readout requirements of the prototype TRD and accurately obtains the energy spectrum of muons and electrons.
Speakers: Mr Jieyu Zhu (Institute of modern physics, Chinese Academy of Sciences), Mr Haibo Yang (Institute of modern physics, Chinese Academy of Sciences), Mr Yangzhou Su (Institute of modern physics, Chinese Academy of Sciences) -
145
High speed readout electronics for new generation Pulsed Muon Spectrometers
The next-generation muon spin spectrometers at the ISIS pulsed source, particularly ‘Super-MuSR,’ are poised to efficiently utilize the increased source intensity, achieving an impressive 1 G·event·hr-1 counting rate. This advancement hinges on the development of highly pixelated, high-density detector arrays covering a significant solid angle, each element fine-tuned for high-rate data acquisition.
Innovative strategies include full digitization of analog waveforms from SiPMs using digital signal processing (DSP), both at the software and firmware levels. This process is realized through the Xilinx Zynq® UltraScale+TM system on a chip, paired with 1 GHz sampling ADCs, leveraging event streaming technology and novel DSP data correction methods.
A critical enhancement is the digitizer's integration of a Kafka node in its firmware, enabling direct data transmission to the readout system and a ZeroMQ-based server for efficient slow control. These features underscore the system's seamless data processing and control capabilities.
Our discussion will explore this concept and its preliminary results, focusing on the prototype digitizing data acquisition system crucial for the 'digital data pipeline' (DDP). This advancement not only marks a technological milestone in detector design and data processing but also heralds new research avenues in muon spin spectroscopy.Speaker: Francesco Caponio (Nuclear Instruments SRL) -
146
High-throughput Custom Monitoring for the Mu2e TDAQ System
This talk describes the use of programmable network hardware to provide a custom monitoring capability for the Mu2e Trigger and Data Acquisition System (TDAQ) system. This system is being designed as part of research that supports the design and deployment of specialized network support for physics experiments.
The goal of the Mu2e experiment is to search for a charged-lepton flavor violating processes where a negative muon converts into an electron in the field of an aluminum nucleus. The TDAQ system of the Mu2e project consists of the detector’s read-out controllers (ROC) that stream digitized readings through a commodity Ethernet network to reach Data Transfer Controllers (DTC), which consist of a commercial, PCIe FPGA card attached to commercial, off-the-shelf (COTS) servers.
The custom Mu2e header format contains a series of bit-fields that are used to convey information about error states at ROCs. At full line rate, we parse and examine these fields and update registers on the switch dataplane to count the errors we observe, and for which parts of the detector they are being observed. This information is periodically relayed to the switch controller, and used to populate a dashboard to alert operators.
We have a working prototype of the monitoring system described in earlier sections, and the next steps for this work include generalizing this monitor to support the detection of other conditions and support their processing in the network’s dataplane.
Speakers: Mr Sean Cummings (Illinois Institute of Technology), Michael H L Wang -
147
Hi’BT : a pixel sensor-based heavy-ion beam telescope for ion-track localization at HIAF
Abstract: The advancement of beam telescopes plays a pivotal role in propelling innovations in particle accelerators and refining detection systems. This research explores the architecture and performance attributes of the Hi’BT (Heavy-ion Beam Telescope) system, a pivotal tool for the forthcoming High-Intensity heavy-ion Accelerator Facility (HIAF) in China. At the heart of the Hi'BT design is the Topmetal-M sensor, which is able to achieve spatial accuracy in the micron range. Further empirical assessments are currently being conducted to corroborate the distinguished performance of the system.
Speaker: Dr Honglin Zhang (Institute of Modern Physics, CAS) -
148
Hybrid Scrubber of SEM and Picoblaze for FPGA on COMET Read-out Electronics
The COMET experiment at J-PARC aims to search for the neutrinoless transition of a muon to an electron ($\mu$-$e$ conversion). We have developed the readout electronics board called ROESTI for the COMET straw tube tracker. We plan to install the ROESTI near the detector, where the neutron fluence is expected on the order of $10^{12}$ neutron/cm$^2$. Neutron-induced single-event upsets disrupt the correct operation of the FPGA. We developed a novel hybrid scrubber of the Xilinx Soft Error Mitigation (SEM) and Xilinx soft microprocessor (Picoblaze) for the FPGA on the ROESTI.
The hybrid scrubber can correct both single-bit and multi-bit upsets in a frame, even without a reference memory that stores the original configuration data. Single-bit upsets are corrected by the SEM. When multi-bit upsets occur, the FPGA communicates with a DAQ PC via TCP/IP and receives the address of bit upsets. The bits at that address are inverted by the Picoblaze. As a result, the bits return to their original state and the multi-bit upsets are corrected.
The neutron irradiation tests were performed with the FPGA that implemented our hybrid scrubber. A total of 25 multi-bit upsets occurred, and all of them were corrected. This result indicates that the time required for FPGA firmware re-download can be reduced by around 76% compared to a conventional FPGA that implements the SEM only.
In this presentation, we will describe the implementation of the hybrid scrubber in the FPGA and the result of the neutron irradiation test.Speaker: Eitaro Hamada -
149
Measurement Module of Dispersion Interferometer for Real-Time Plasma Density Control at Globus-M2 Tokamak
The report is dedicated to a measurement module of a dispersion interferometer for plasma density control at Globus-M2 tokamak (St. Petersburg, Russia). The system provides measuring of integral plasma density with resolution of 4·10^15 m^-2 every 20 μs. Such characteristics of the device allow using the results of its measurements in а feedback loops to real time plasma density control. The main elements of the measurement module are analog-to-digital converters and a digital data processing node based on SoC FPGA. The algorithm for plasma density calculating is implemented in the digital node. This algorithm bases on harmonic analysis of interferometer signals and it is resistant to noise and changes of modulation depth. The dispersion interferometer combined with the measurement module was installed at Globus-M2 in 2022. During the year operation, this system was proven to be reliable and robust diagnostic for line-integrated electron density measurements. The first experiments for controlling the electron density using dispersion interferometer as a detector were carried out at Globus-M2 in November 2023.
Speaker: Dr Svetlana Ivanenko (Budker Institute of Nuclear Physics SB RAS) -
150
Methods for On-Orbit FPGA Firmware Update and Verification Based on FLASH
In space applications, firmware updates play a crucial role, ensuring that payloads in orbit can acquire new functionalities or rectify logical errors. Stable and efficient updates are essential. Concurrently, high-energy charged particles in space can affect electronic components. Single Event Upsets (SEUs) may alter the logic state of digital circuits. If an SEU occurs in the FLASH storing the firmware, it could potentially impact payload operations.
We've engineered a firmware update method tailored for commercial-grade FLASH: issuing update commands via the CAN 2.0 bus, transmitting firmware data through Ethernet, ensuring accuracy with CRC-32 and ECC verification during transmission and FLASH writing, and featuring data retransmission capability. Additionally, a backup firmware in FLASH guarantees update retries upon failure. Using Xilinx's XC7K70T, updates conclude within 2 minutes, ensuring data accuracy. Addressing potential single-event upsets affecting FLASH integrity, we routinely extract firmware data and compute 8-bit, 16-bit, and 32-bit checksums in orbit. Ground simulations confirm the effectiveness of these checksums in verifying data integrity.
The Cosmic X-ray Polarization Detector (CXPD) is designed as a highly sensitive soft X-ray polarimeter carried by a CubeSat, capable of measuring energy within the range of 2 to 10 kilo-electron volts. Its electronic system (CXPDES) not only enables on-orbit telemetry, telecommand, and data transmission but also boasts the ability to conduct on-orbit firmware updates. Through ground testing, we performed firmware updates over a hundred times without encountering any update errors. Currently, the CXPDES has been operational in orbit for 175 days and has successfully completed one firmware update.
Speaker: Ran Chen (Central China Normal University) -
151
Nupix-H1, a MAPS for real time beam monitoring at HIAF
In past decades, scientists have made many outstanding achievements in nuclear physics, nuclear astrophysics and atomic physics, biomedicine, and other fields based on accelerators. In order to promote the development of heavy ion accelerator technology and improve the research level, the next generation of the heavy ion research facility, HIAF, has been proposed. The beam energy of HIAF will reach GeV, and its operation is inseparable from the support of the beam monitoring system. The Nupix-H1, designed for the real time beam monitoring system in HIAF, has excellent position resolution and energy resolution and can simultaneously measure the energy and time information of the hit particles. Nupix-H1 includes a 64x64 pixel array, a pixel bias circuit, an analog buffer, and a digital scan readout circuit. Nupix-H1 can measure the deposition energy up to 5ke−, with ENC better than 15e− and INL better than 2.24%. The time measurement range is 22µs, and the maximum INL is 2.54%. In addition, we proposed an AC coupling method to increase charge collection efficiency.
Speaker: Hong Yuan (Institute of Modern Physics, CAS) -
152
Nupix-H2: a Monolithic Active Pixel Sensor for Multidimensional Measurement
The Heavy Ion Research Facility in Lanzhou (HIRFL) and the High Intensity Heavy-ion Accelerator Facility (HIAF) are leading platforms for heavy ion scientific research in China. Based on them, the Electron-ion collider in China (EicC) is under construction to represent a new generation of physics experiments. These scientific facilities have led to the development of advanced detectors. Monolithic Active Pixel Sensor (MAPS) is a type of sensor with high spatial resolution, low noise, and low power consumption, and it is widely used in vertex and tracking detectors. A MAPS called Nupix-H2 designed in GSMC 130 nm quadra-well process can measure the particle hit's position, energy, and arrival time. This chip comprises a 128-row and 128-column pixel matrix with a pitch of 28.705 µm. Each pixel utilizes a Charge Sensitive Amplifier (CSA) structure to achieve energy measurement, coupled with a comparator and a shared counter for 16 pixels to achieve time measurement. With a novel automatic reset scheme of each pixel, the Nupix-H2 can work in a continuous mode. It achieves an Equivalent Noise Charge (ENC) of 21e- in the input range of 100 e- - 10 ke-, a maximum INL of 2% of the energy path output, and the conversion gain is approximately 55 µV/e-. With a 40 MHz clock used for the counter, the time resolution can reach close to 25 ns.
Speaker: Ms Rui He (Institute of Modern Physics, Chinese Academy of Sciences) -
153
Optimization of Energy Resolution in Topmetal-ii- Pixel Detector: An Exploration of Neural Network and Curve Fitting Strategies
This study aims to optimize the energy resolution of the Topmetal-II pixel detector through the utilization of neural networks and curve-fitting strategies. The Topmetal-II plays a crucial role in capturing soft X-ray signals, enhancing its energy resolution is crucial for accurate measurements.
We employed neural networks, specifically Convolutional Neural Networks (CNNs), to train on the energy data of Topmetal-II, aiming to enhance its performance. Simultaneously, we employed curve-fitting techniques to model the response of Topmetal-II. Through the fitting of mathematical curves to the detector's energy response, our objective was to optimize its performance and improve energy resolution.
We employed a 12-bit ADC for the continuous acquisition of the energy channel of the Topmetal-II. The final statistical results indicate that adopting a neural network structure, with encoding and decoding layers each comprising 5 layers and 2 fully connected layers, along with the use of a Denoising AutoEncoder (DAE), yielded promising results. A comparison between DAE outputs and inputs showed a reduction in RMSE from 0.0447 to 0.0132, a decrease by a factor of 3.38, resulting in a 9.54% improvement in energy resolution. In curve fitting, the output function of the charge-sensitive amplifier was employed for data fitting. The RMSE decreased from 0.05385 to 0.01423, a reduction by a factor of 3.78, leading to an 11.1% enhancement in energy resolution. These results robustly support the progression of soft X-ray detection technology, indicating the potential for delivering more precise and reliable measurement outcomes in low-energy polarization detector (LPD) experiments.Speaker: Ni Fang -
154
Prototype Design of Data Converter Module for LLRF Applications
In modern accelerator applications, stringent requirements are placed on the noise performance of digital converters. The noise from the digital converter will become part of the field noise seen by the beam, thus necessitating a low-noise, low-crosstalk digitizer. In response to this demand, this paper presents the design of a digital converter circuit board with 8 ADC channels and 2 DAC channels, which has been subjected to testing. The test results indicate that the circuit board possesses low noise and low crosstalk characteristics, rendering it suitable for reading accelerator signals.
Speaker: Mr Qiutong Pan (Tsinghua University) -
155
Prototype Design of Readout Electronics for the Multiple Sampling Ionization Chamber at HIAF - HFRS
Nuclear physics with radioactive beams has been the most dynamic frontier research field in nuclear science. The high intensity heavy-ion accelerator facility (HIAF) under construction is equipped with a high energy fragment separator (HFRS), characterized by high energy and high intensity. HFRS utilizes the Bρ-TOF-ΔE method for high magnetic rigidity, large ion-optical acceptance, and excellent particle identification, commonly used in nuclear fragmentation secondary beam devices. Among them, the energy loss detector ΔE is the key to particle identification. The energy loss detector is designed using the multiple sampling ionization chamber (MUSIC). It can significantly improve the energy resolution of the gas ionization chamber through multiple samplings. The readout electronics of the MUSIC consist of 16 charge sensitive preamplifiers (CSP) modules and two readout control electronics (RCE) modules. A single RCE has eight channels. The CSPs, placed inside the MUSIC, read out the MUSIC charge signals. The RCE receives the voltage pulses from the CSP, performs voltage signal amplification and filter, and digitizes the signal. The measured data is packed and transmitted to the DAQ system with a 10 Gb ethernet protocol. Comprehensive tests have been performed on the readout electronics. The test results indicate that the noise performance is less than 1.8 ADC values (RMS), and the nonlinearity of the full readout electronics is less than 0.17%. In addition, radiation source test results demonstrate that the readout electronics can reach good performance. We are preparing for beam experiments to further evaluate the performance of MUSIC and the electronics system.
Speakers: Dr Haibo Yang (Institute of Modern Physics, Chinese Academy of Sciences), Mr Xianqin Li (Institute of Modern Physics, Chinese Academy of Sciences), Prof. Chengxin Zhao (Institute of Modern Physics, CAS) -
156
Real Time Data Acquisition for PET Detector Evaluation based on dual-polarity Charge-to-Digital Converter
Silicon photomultiplier (SiPM) was increasingly applied in nuclear medicine imaging development in recent years, especially in positron emission tomography (PET) scanner. To achieve a cost-effective, power-efficient signal processing unit for the SiPM array, a compact 128-channel front-end electronic (FEE) system based on dual-polarity charge-to-digital converter (dQDC) was proposed. A dQTC circuit consists of two resistors, a commercial amplifier, an integration capacitor, a voltage-referenced receiver and a discharging I/O pin in the FPGA. The hardware of the 128-channel FEE consists of an analog board and an FPGA board. In the analog board, 128 channels of dQDC analog circuits are implemented. The FPGA board is based on a low-cost FPGA, instantiating 128 LVDS receivers that serve as 128 voltage comparators. The SSTLⅡ standard is used to maximize the dynamic range of the dQTC circuit. The electronics performance of the FEE is evaluated in terms of noise, linearity, and uniformity. A PET detector is used to verify the readout capability of the 128-channel FEE system. The PET detector is made up of a 15×15 lutetium-yttrium oxyorthosilicate (LYSO) array and two SiPMs. The LYSO array is coupled with the two SiPM array at two ends. With the 128-channel FEE, the energy resolution (ER) of the PET detector is about 13.2%, and Peak-to-Valley Ratio (PVR) is 6.02. Currently, a time-to-digital converter is being developed to achieve a high-precision timing measurement for the PET detector. All the results of the performance evaluations including electronics and detectors will be presented in the meeting.
Speaker: Bo Wang -
157
Real Time FFT Calculation Using FPGA PCIe card for KSTAR Magnetohydrodynamic Analysis
A real time data acquisition system is being implemented using a configurable muti-functional FPGA PCIe card. The FPGA card acquires 16 channels signal at 250 kHz, calculates 512-point Fast Fourier Transform (FFT), and provides the full data set of both original raw data and FFT derived data to the real-time computer. Data is recorded to the Korea Superconducting Tokamak Advanced Research (KSTAR) MDSplus database outside of plasma control system (PCS) for analysis and internal to PCS for algorithm use. Part of the real time version of disruption event characterization and forecasting (DECAF) running inside PCS uses this input for internal calculations.
When constructing the FFT engine in hardware, Intel FFT IP core is used to implement FFT. The detailed pipelining and timing for 16 channel 512 sample points for the FFT engine is described in the paper. Dual FIFO and RAM ping pong architecture are used for data reading, processing, and writing. The test result shows that the pipelined FFT engine works as expected. This work was supported by DOE contract No. DEAC0209CH11466 and grant DE-SC0020415.Speaker: Mr Weiguo Que (Princeton Plasma Physics Laboratory) -
158
Research and Application of SIMD-Based Online Data Processing Acceleration Technology
Intel AVX-512 is a Single Instruction Multiple Data (SIMD) instruction set based on x86 data center processors. Unlike traditional Single Instruction Single Data operations, a SIMD instruction can simultaneously execute operations on multiple data, effectively accelerating compute-intensive tasks. This feature is well-suited to the requirements of online data acquisition and processing in physical experiments. For example, during the data acquisition for pixel detectors, real-time image processing and optimization are essential to ensure image quality and accuracy. However, this process often demands substantial CPU computational resources within the system. By utilizing SIMD technology based on the AVX-512 extension instruction set to vectorize the code, the program's execution performance has been effectively improved, resulting in resource savings and enhanced system integration. Furthermore, this technology is applied to accelerating a software-based multiplicity trigger algorithm proposed in this paper, thereby achieving superior performance.
Key Words: AVX-512; SIMD; High Performance Computing; Image Processing; Software TriggeringSpeaker: Mr Pengfei Xiao -
159
Study of Decoupler: Empowering FPGA Debugging with ESP32 and IoT
The significance of the remote debugging capability cannot be overstated when it comes to separating the urgency of FPGA-based hardware deployment from the maturity of firmware design. Furthermore, the importance of sensor monitoring in the success of complex systems like TDAQ in high-energy physics experiments is evident, even though it presents fewer challenges compared to the TDAQ system itself. The integration and processing of data from diverse sensors remain a critical focus.
This research introduces an innovative solution known as the "Decoupler," specifically designed to address key challenges in FPGA-based systems, especially during the initial stages of firmware development and sensor monitoring.
The Decoupler utilizes an ESP32-based module with a slight modification to the JTAG connector pinout. It implements an xvc server for remote debugging and connects to an IOT-HUB for sensor data collection and control. This approach eliminates the need for additional hardware space and firmware resources. Notably, it simplifies integration and maximizes the utility of existing hardware. By leveraging the JTAG's Vref for power, the ESP32 module doesn't require an independent power supply and can operate in an ultra-low-power mode when debugging is unnecessary, conserving energy while still delivering near-real-time sensor data transmission.
Its ability to function independently of the FPGA's firmware development process and its utilization of existing JTAG connectors for both power and data transfer mark a significant advancement in the field.Speaker: Yifan Yang (Universite Libre de Bruxelles (BE)) -
160
Study on the Design and Production of a Prototype Liquid Level Detection Equipment Utilizing Geiger-Muller Detector
The article discusses a research presentation on the design and manufacture of handheld radiation measurement devices using Geiger-Muller tubes counting gamma radiation, applied in educational settings. The research and development aim to support educational training, aiding students in comprehending the interactions of radiation with matter, contributing to the dissemination of knowledge about atomic energy applications, and enhancing the quality of presentations at the Nuclear Research Institute Training Center. Initial results have led to the creation of a portable radiation measurement device utilizing Geiger-Muller tubes and a 10µCi Cs-137 gamma source, displaying the count on a 16×2 LCD screen, and powered by a 9VDC supply for ease of use and safety. This serves as a foundation for further research in developing radiation measurement devices using X-rays, with the goal of enhancing the visual and vivid aspects of lectures on atomic energy applications. The objective is to use gamma transmission methods without relying on complex and expensive equipment, ensuring radiation safety at the Training Center.
Speaker: Mr Dang Quoc Trieu (researcher) -
161
Synchronization between detector and motion axes in a neutron instrument
The single crystal hot neutron diffractometer HEiDi is operated by Forschungszentrum Jülich at the research reactor FRM II in Garching. Core of the instrument is the 4-circle diffractometer, consisting of an Eulerian cradle for the sample and the detector arm. The detector of HEiDi is a single a 3He detector tube. In classical scans, in each step the axes of the 4-circle diffractometer are moved to the desired position and then the measurement is started. A reduction of measurement time can be achieved by measuring also during movement. The necessary synchronization between the motion subsystem and the detector is being implemented. The motion subsystem is based on a Siemens S7-1500 PLC and the synchronization uses its cam track technology objects.
Speaker: Harald Kleines -
162
The front-end electronics of the Hyper-Kamiokande far detector
The Hyper-Kamiokande (Hyper-K) experiment is a next generation underground water Cherenkov detector designed to search for leptonic CP-violation and a wide science program, including neutrino astrophysics, and searches for nucleon decay.
The main photo-sensor used in the experiment is the 20" box-and-line R12860 PMT, an improved version of the ones used in Super-Kamiokande. Due to the tank size in Hyper-K, the electronics will be placed underwater to minimize the length of the photomultiplier cables. Because of this and the new PMT models, a new signal readout system had to be developed.
The requirements for this new digitizer are the possibility to set the trigger threshold to a 1/6 of p.e., a maximum signal rate of more than 1MHz (in case of supernova and electrons from decay of muons) and a power consumption of less than 1 W per channel.
The final design has 12 single channels made of discrete electronic components. Each channel has an input receiver that sends the signal into two different paths: one that creates a digital trigger and the other that goes to an integrator and then to two ADCs that measure the signal charge. To collect the data from the 12 channels the board is equipped with a Xilinx Kintex-7 FPGA, that will also measure the Time-over-Threshold and Time-of-Arrival.
The whole board mounts a switching power supply custom designed to generate all the voltages needed by the components present on the board.
The design is almost complete and will be finalized in 2024.Speaker: Alessandro Di Nola (Universita Federico II e INFN Sezione di Napoli (IT)) -
163
The HIPA radio frequency control system application
For the upgrade of the High Intensity Proton Accelerator at PSI of injector cavities 2 and 4, a new digital radio frequency control system was developed using the IFC 1210 VME board. This system comprises three components: A single-board computer running the control system software and the real- time application, both running on a dual core P2020 PowerPC, as well as the FPGA Design utilizing a Virtex 6. The real-time application (RTAPP) covers three use cases: "Cavity Tuning”, “Startup FSM”, and “Calculate Statistics”. “Cavity Tuning” implements the controller for the cavity’s tuning system, which consists of two controllers. One controls the physical position of the two tuners within the cavity, and the other one provides the setpoint for the tuner controller and controls on the phase error between forward power and cavity pickup, ensuring minimum reflected power during operation. The “Startup FSM” governs the radio frequency control system during the startup procedure. Here, the cavity must overcome the multipactoring zone while minimizing reflected power and without overstressing the amplifiers. Finally, “Calculate Statistics” performs computations on measurement data from high resolution ADC RAW values, reducing the data load before forwarding them to the control system. The software design is split into four layers: Common, hardware, service and application layer. These layers cover 13 different components which are each assigned a dedicated thread. The update frequency of the components varies between 25 and 50Hz, real-time behavior is given if a deadline of 20ms or 40ms respectively can be guaranteed.
Speaker: Mario Jurcevic -
164
The IMPix-S2, a hybrid pixel readout ASIC for beam monitoring
The Heavy Ion Research Facility in Lanzhou (HIRFL) and the High Intensity Heavy-ion Accelerator Facility (HIAF) are advanced heavy-ion accelerators, which play a critical role in pursuing a deeper understanding of nuclear physics. The beam monitoring system, known as the eyes of the accelerators, is an essential part of the accelerator facilities. Its function is to monitor the beam parameters to improve the beam quality. The performance of the beam monitoring system determines the ability of researchers to enhance the quality of the beam. The Topmetal silicon pixel ASIC IMPix-S2 is a hybrid pixel readout ASIC independently developed by us. It can directly collect the space charge around the chip without interaction with particles, and is the core device of the beam current monitoring system. The IMPix-S2 was designed using a 0.13 μm process with an ASIC size of 23 mm × 2.24 mm for beam monitoring. The ASIC mainly consists of a sensitive area consisting of circuits such as pixel arrays and a non-sensitive area for readout control. The sensitive area has 16 banks of pixels, each bank has 28 rows × 48 columns of 29 um × 29 um pixels. Each pixel measures the energy of the collected charge by topmetal, CSA, peak-holding circuit and source follower circuits. The readout control adopts a rolling shutter scanning method, where each bank scans all its pixels simultaneously and sequentially to output the energy information off-chip.
Speaker: xiaoyang Niu -
165
The Software Platform of LabVIEW-FPGA-Based Real-time Processing System in Keda Torus eXperiment
We implemented A LabVIEW-FPGA-Based Real-time processing system for Keda Torus eXperiment (KTX) as a part of Active Control Feedback Electronics System (ACFES). The processing system plays a role in real-time feedback control and communication between KTX central control system and hardware devices of ACFES.
Experiment results prove that the designed system provides a real-time data acquisition and feedback, offers convenient interact between CSS-Host-Slaves and can help ACFES hardware devices work perfectly, as a consequence, remarkably extends the discharge time of KTX.
We will briefly metion the hardware architecture and introduce the modularized software platfrm combined with the acquisition and aggregation FPGA logic.Speaker: Jiahong Jiang (University of Science and Technology of China) -
166
Thermal neutron induces Single-Event Upsets in the FPGA used in particle physics experiments
Many particle physics experiments utilize FPGAs in intense radiation environments, and they are concerned about SEUs. An SEU is a soft error that occurs when a charged particle plunges into the part of an SRAM or flip-flop that holds the data. Neutrons also have the possibility of causing SEUs because they can generate charged particles by interacting with atoms in semiconductor devices. We investigated SEUs particularly caused by thermal neutrons. The study employs a 28-nm CMOS FPGA from Xilinx Inc., implementing Soft Error Mitigation (SEM) Controller firmware to detect and correct SEUs. We performed a neutron irradiation test at the tandem accelerator to measure SEUs in various settings, including shielding with polyethylene blocks or ones containing Boron trioxide. To measure the fast- and thermal-neutron doses separately, we used a solid-state track detector CR39 (allyl diglycol carbonate). Results show successful reduction of fast neutrons in certain settings, affirming control measurements and we concluded thermal neutrons caused SEUs. In this presentation, we report details on the SEUs in FPGAs caused by thermal neutrons.
Speaker: Chihiro Yamada (Osaka University) -
167
Track reconstruction for the ATLAS Phase-II High-Level Trigger using Graph Neural Networks on FPGAs
The High-Luminosity LHC (HL-LHC) will provide an order of magnitude increase in integrated luminosity and enhance the discovery reach for new phenomena. The increased pile-up foreseen during the HL-LHC necessitates major upgrades to the ATLAS detector and trigger. The Phase-II trigger will consist of two levels, a hardware-based Level-0 trigger and an Event Filter (EF) with tracking capabilities. Within the Trigger and Data Acquisition group, a heterogeneous computing farm consisting of CPUs and potentially GPUs and/or FPGAs is under study, together with the use of modern machine learning algorithms such as Graph Neural Networks (GNNs).
GNNs are a powerful class of geometric deep learning methods for modeling spatial dependencies via message passing over graphs. They are well-suited for track reconstruction tasks by learning on an expressive structured graph representation of hit data and considerable speedup over CPU-based execution is possible on FPGAs.
The focus of this talk is a study of track reconstruction for the Phase-II EF system using GNNs on FPGAs. We explore each of the steps in a GNN-based EF tracking pipeline: graph construction, edge classification using an interaction network (IN), and track reconstruction. Several methods and hardware platforms are under evaluation, studying optimizations of the GNN approach aimed to minimize FPGA resources utilization and maximize throughput while retaining high track reconstruction efficiency and low fake rates required for the ATLAS Phase-II EF tracking system. These studies include IN model hyperparameter tuning, model pruning and quantization-aware training, and sequential processing of sub-graphs over the detector.
Speaker: Santosh Parajuli (Univ. Illinois at Urbana Champaign (US))
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107
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12:55
Lunch
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Oral Presentations: Orals
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168
Current status and future development of ASICs for HIAF complex
The Heavy Ion Research Facility in Lanzhou (HIRFL) and the High-Intensity Heavy-ion Accelerator Facility (HIAF) are leading platforms for heavy ion scientific research in China. Several physics experiments are being under construction at HIAF, such as the Electron-ion collider in China (EicC), the China Hyper-Nuclear Spectrometer (CHNS), the High energy FRagment Separator (HFRS), etc. Developments of Application Specific Integrated Circuits (ASICs) are critical for the physics experiments at HIAF. This paper will introduce the current status and future development of ASICs for the HIAF complex. This paper discusses the current status and future plan of the ASICs development, including the front-end readout ASIC for silicon strip detectors, silicon pixel detectors, TPC detectors, TOF detectors, and LGAD detectors. In addition, we will also present design of the high-performance ADCs and high-speed SERDES.
Speaker: Prof. Chengxin Zhao (Institute of Modern Physics, CAS) -
169
Development of Radiation-tolerant Slow-Control Board based on Atom Switch-based FPGA
Atom Switch-based FPGA (AS-FPGA) is a potential candidate for use in high radiation environments like future particle physics experiments using accelerator. We performed neutron and gamma-ray irradiation tests for the AS-FPGA. No Single Event Upsets (SEUs) were found at least up to 10$^{11}$ and 10$^{12}$ n/cm$^2$ with and without applying voltage, respectively. It tolerated Displacement Damage Doses (DDDs) at least up to 10$^{14}$ n/cm$^2$ and showed no Total Ionizing Dose effects (TIDs) at least up to 2 and 5 kGy with and without applying voltage. We confirmed the suitability of the AS-FPGA for such environments. More tolerances for SEUs, DDDs, and TIDs for higher radiation levels are expected, and these tests are ongoing. To apply the AS-FPGA realistically to the experiment, some evaluations and improvements are needed. We have developed an evaluation board for slow control to assess performance. It was used for logic, function, and operational tests under irradiation, and we have successfully operated the AS-FPGA in the high radiation environment. In this presentation, we report more details about the irradiation tests of AS-FPGA and the development of the slow-control board.
Speaker: Kazuki Ueno (Osaka University) -
170
Study of Dynamic Time Over Threshold (DTOT) method for application in spectroscopy signal analysis toward a low complexity front-end electronics with high spectroscopy resolution and wide energy range for use with scintillation gamma detectors
Traditional approach of spectroscopy signals acquisition and analysis comprises digitization performed ideally by a high bit resolution and short sampling period flash ADC, followed by a subsequent digital processing requiring a high computational performance. However, some particular applications cannot implement that traditional approach while demanding comparable high spectroscopic performance due to hardware limitations mainly given by operational conditions, availability of qualified electronic components, power consumption limit, etc. The Dynamic Time Over Threshold (DTOT) conversion method based processing of spectroscopy signals represents an undemanding alternative in contrary to that traditional approach. The detailed study of different profiles of the dynamic threshold signal was performed in order to reveal their impact on performance of the DTOT conversion and to maximize dynamic range and to extend an acceptable span of input spectroscopy signals. The contribution also presents practical implementation of front-end electronics integrating DTOT converter dedicated for SiPM based gamma detectors while test measurements with common reference radiation sources was performed in order to provide comparative results.
Speakers: Dr Michael Holik (IEAP CTU in Prague, FEE UWB in Pilsen), Ondrej Urban (University of West Bohemia (CZ)) -
171
A High Compression Ratio Channel Multiplexing Method for Micro-pattern Gaseous Detectors
Micro-pattern gaseous detectors (MPGDs) find wide-range applications in particle physics experiments, industry, and medical imaging, owing to their large area, fine spatial resolution, and relatively low material content within the sensitive region. However, the requirement of a large number of readout channels poses a challenge, limiting the application of MPGD to achieve higher accuracy and larger area. This requirement also presents significant challenges regarding system integration, power consumption, cooling, and cost. Previous studies have shown that, under sparse effective hits, a channel multiplexing method based on position encoding can address this issue. Nonetheless, improving the compression ratio and addressing the high event rate problem remain key challenges requiring further investigation.
In this research, we have developed two types of high compression ratio multiplexing methods and their mathematical models. It is shown that a maximum of $n(n-2)/2+2$ detector channels can be read out with n electronics channels if n is even. Using these methods, several multiplexing boards were designed and implemented. Considering the real condition of the detectors, we achieved an encoding board with 64 readout electronics reading out 1024 detector channels, marking the highest compression ratio in current research. Additionally, we developed waveform digitization front-end electronics to address the high event rate problem. Different events can be distinguished and properly decoded by introducing the signal arriving time. Moreover, these encoding circuits were utilized and verified in our cosmic-ray muon imaging facilities, demonstrating their advantage of reducing the required number of front-end electronic cards.
Speaker: Dr Yu Wang (University of Science and Technology of China) -
172
System Design and Prototyping of the CMS Level-1 Calorimeter Trigger at the High-Luminosity LHC
The High-Luminosity LHC (HL-LHC) proposes an ambitious physics program covering high-precision Standard Model (SM) measurements and advancing the searches for new physics. The efficient data gathering and precise events reconstruction in the intense environment of 200 proton-proton interactions per bunch-crossing (40 MHz) are essential for attaining the success of the HL-LHC program. To fulfill these requirements, the CMS experiment is building an entirely new data acquisition (DAQ) and trigger systems. The Phase-2 CMS Level-1 trigger system will drive the massive detector input data bandwidth of 75 Tbps and is aimed to complete the single event processing within 12.5 $\mu$s. For this purpose, CMS plans to replace the Phase-1 $\mu$TCA-based processor cards and crates with an ATCA specification. Each ATCA board is powered with Xilinx UltraScale+ family FPGA that supports over a hundred high-speed optical links at 25 Gbps, capable of handling the high bandwidth and processing requirements of the HL-LHC. Along with the upgrade in hardware, the Level-1 trigger system will use highly flexible, modular, and adequately sophisticated algorithms currently feasible solely in offline reconstruction, such as a particle-flow (PF) algorithm. The flexible and modular architecture will assist in addressing the HL-LHC physics requirements. This talk will discuss the system design, prototyping, and algorithms being developed for the Phase-2 Level-1 Calorimeter trigger system.
Speaker: Piyush Kumar (University of Hyderabad, India) -
173
Check-Sort-Push and its application in CMS iRPC subsystem
Nowadays backend electronics has been used with help of unified high speed link to provide the fast control and slow control (electronics parameter setting) to frontend electronics in addition to providing trigger preprocessing and data readout. In such a case, the link is normally shared by many front channels, the processing time in backend for those channels with low readout priority, varies tremendously especially when in high rate or occupancy case, even with the zero-suppression and Multiplexing in FEE before the transmission, which make the processing (DeMux and trigger pre-processing) latency unpredictable or unacceptable. This presentation addresses this issue with simulation study and our Check-Sort-Push proposal to provide a solution to this, the necessity and advantage of this proposal over other ones with simulation/emulation results in high occupancy/high hit rate cases, and its firmware implementation both on the transmitter FEE and receiver BEE sides will be given. Application of this Check-Sort-Push in the improved RPC system(iRPC) in CMS phase II upgrade, with be provided as well as the analysis results from the cosmic ray test and beam test data taking.
Speaker: Prof. Zhen-An Liu (IHEP,Chinese Academy of Sciences (CN)) -
15:50
Coffee Break
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174
Invited Talk: Mastering Picosecond Precision: Lessons learned from Large-Scale Timing Systems
The MEG II experiment, based at PSI in Switzerland, aims to detect rare muon decay events. A critical aspect of this experiment is the precise measurement of the timing of both the calorimeter and timing counters, achieving accuracy within a few picoseconds. This precision is made possible by employing the DRS4 Switched Capacitor Array ASIC alongside a sophisticated timing system. This system integrates a custom crate standard to ensure synchronization across more than 30 crates, encompassing over 9000 channels.
The presentation will focus on the practical insights gained from designing and operating such an extensive system over several years. Key areas of discussion will include strategies for clock generation and distribution, methods for jitter reduction, the impact of noise, and techniques for global time calibration. The experiences and lessons learned from this endeavor will be shared in a manner that is highly relevant and transferable to other experiments striving to achieve optimal timing precision.
Speaker: Stefan Ritt (Paul Scherrer Institute) -
175
Development of first level track trigger at Belle II using Deep-Neural-Network
The Belle II Experiment, located in Japan with the SuperKEKB, an energy-asymmetric electronpositron collider, is the next generation of B-factories. SuperKEKB targets a luminosity of $6× 10^{35}\text{cm}^{-2} \text{s}^{-1}$, enabling unprecedented new physics investigations and Standard Model parameters measurements.
However, the increase in luminosity faces escalating challenges, notably in the realm of level1 triggers. The level-1 trigger, implemented in deadtime-free pipelined hardware, performs online event reconstruction to mitigate substantial beam-induced background and identify signal events. It imposes stringent criteria for level-1 trigger, encompassing a latency under 5 μs, high efficiency, and a prerequisite for trigger rate below 30 kHz, which already reached unexpectedly 10 kHz at a luminosity of $4.7×10^{34}\text{cm}^{-2}\text{s}^{-1}$. To tackle this challenge, this work introduces a novel Deep Neural Network (DNN) in the level-1 trigger system.
This work focus on the Central Drift Chamber (CDC) trigger system, responsible for reconstruction for charged tracks and rejecting the major beam background originating off the interaction point. The current CDC trigger, based on a single hidden layer neural network architecture, demonstrated approximately 95% efficiency with about 50% background suppression. We have developed a new track trigger with an optimized DNN architecture for fitting and classifying charged tracks, achieving an impressive 80% beam background suppression in simulations.
The DNN track trigger is implemented to Field Programmable Gate Array incorporates parallelized processing, reduced routing congestion, and optimized resource and latency consumption, utilized the newly deployed fourth-generation universal trigger board. In this talk, we present the simulation and hardware implementation for the DNN track trigger.Speaker: Yuxin Liu (KEK) -
176
High-Throughput Data Analysis at FRIB using ESnet
With the beginning of the Facility for Rare Isotope Beams (FRIB) era, data acquisition systems and analysis tools are required to keep up with new detector technologies for higher data rates and volumes. Recent upgrades to the FRIB Data Acquisition System (FRIBDAQ) enable sustained data throughput of $\approx$200 MB/s. Experiments utilizing this capability write large amounts of data to disk, where nearline analysis methods are critical to inform decision-making by users. The introduction of the Energy Sciences Network (ESnet), a U.S. Department of Energy (DOE) supported high-speed network for scientific research, creates opportunities to leverage the computing power of DOE facilities like the National Energy Research Scientific Computing Center (NERSC). An analysis workflow, successfully demonstrated at MSU's Institute for Cyber-Enhanced Research, was adapted for processing data at NERSC using ESnet to mediate the transfer of data between facilities. A proof-of-principle test was performed using data from the first FRIB experiment. Data was transmitted from FRIB to NERSC where it was processed to measure observables of scientific interest before being transmitted back to FRIB. This workflow demonstrated that a week's worth of experimental data can be analyzed in approximately 90 minutes, a speedup of several orders of magnitude. A summary of the FRIBDAQ upgrades and results from the workflow development will be presented.
This material is based upon work supported by the DOE Office of Science, Office of Nuclear Physics and used resources of the FRIB Operations, which is a DOE Office of Science User Facility under Award Number DE-SC0023633.
Speaker: Aaron Chester (Facility for Rare Isotope Beams) -
177
General-purpose data streaming TDCs for nuclear and hadron experiments in Japan
We have developed a trigger-less data-streaming-type high- and low-resolution TDC called Str-HR(LR)TDC using an AMD Kintex-7 FPGA to develop a general-purpose trigger-less DAQ system in Japan. The trigger-less DAQ system shows promise as a leading candidate of the next standard of the DAQ field in the particle and nuclear experiments. The developed Str-TDCs has been designed for general use, not for a specific experiment. It is implemented on the general-purpose FPGA logic module called AMANEQ [1].
The developed Str-HRTDC consists of two blocks. Timing measurement is outsourced to the FPGA on the mezzanine card of AMANEQ where CARRY4 elements realize tapped-delay-line. The FPGA on AMANEQ collects data from two mezzanine cards and transfers it to a PC via 10-Gbps TCP/IP utilizing SiTCP-XG. For module synchronization, we have adopted the MIKUMARI-link technology [1]. The MIKUMARI is responsible for synchronizing the clock signal frequency and providing the reference timing for TDCs. In addition to its use for the FPGA on AMANEQ, it is also used for the synchronization between AMANEQ and the mezzanine cards. We tested Str-HRTDC by feeding the same input pulse to two synchronized AMANEQs. The obtained timing resolution was 24 ps (σ).
In this contribution, we will present the technical specifications of Str-HRTDC, including its performances, the timing resolution, and the data transfer speed. We will also outline the implementation plan for incorporating Str-TDCs into other front-end electronics as a future prospect.
[1] R. Honda, IEEE TNS, 70 (6), 1102 (2023).Speaker: Ryotaro Honda (KEK IPNS) -
178
100 Gbit/s UDP Data Acquisition on Linux using AF XDP: The TRISTAN Detector
A growing number of detectors produce data rates of more than 100 Gbit/s, which often necessitate software-defined data processing to operate. Because of its simplicity, UDP offers a straightforward method for integrating such detectors with online computing resources that host the data processing software. Nevertheless, conventional technologies—such as POSIX sockets—are either ineffective or difficult to apply on detector boards based on FPGAs, like RDMA. The new Linux sockets AF_XDP are a novel method that uses RDMA-like zero-copy methods to target high data speeds. In this paper, we present a DAQ framework based on AF_XDP and UDP for readout systems with more than 100 Gbit/s. We evaluate our framework for the TRISTAN detector whose rates are expected to reach 200 Gbit/s. We describe our experience developing a TRISTAN detector readout system using AF_XDP.
Speaker: Jalal Mostafa
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168
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19:00
Conference Dinner
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Oral presentations, CANPS Award
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179
Evaluation of SmartNIC Devices for use in Trigger and Data Acquition Systems
This contribution presents an evaluation of SmartNIC devices in the context of Trigger and Data AcQquisition (TDAQ) systems. SmartNIC devices represent an emerging technology whose aim is to offload network tasks and infrastructure control plane software from the CPU. Such devices are particularly relevant for TDAQ systems where high rates in the orders of TB/s are produced in large detectors such as the DUNE experiment. In this context, the potential use-case of SmartNICs is to perform a quasi real-time reduction of the incoming data streams by identifying only the interesting signals. The goal is to sustain a number of ∼10 Gb data streams aggregated on 100 Gb interfaces, and transmit the results to the host machine.
An application was developed to provide a testing environment, measuring the achieved throughput in two cases. In the first case, only the total throughput is considered, and the workload is evenly distributed across the available hardware. In the second case, a constraint of processing a number of discrete data streams is added. The application was shown to handle up to ∼130 Gbps of incoming data when distributing the workload evenly on the available hardware resources of 8 CPU cores. In this contribution, we show the testing results and optimizations and hardware tuning of the technology when performing a workload suitable for TDAQ applications.
Speakers: Adam Abed Abud (CERN), Andreas Klavenes Berg (Norwegian University of Science and Technology (NTNU) (NO)), Enrico Gamberini (CERN), Roland Sipos (CERN) -
180
Test and data acquisition software for CPV-4
Abstract: Combining 3D vertical integration technology with SOI pixel process, the CPV-4 chip integrates sensing diode and analog front-end functions into the lower-tier chip, while hit information storage and readout functions are implemented in the upper-tier chip. This reduces pixel size and power consumption, thereby enhancing the spatial resolution of the detector. Due to the complexity of the SOI-3D process, a more flexible and reliable readout system is required to test the performance of the chips. Therefore, the development of the CPV-4 chip data acquisition system is completed using the IPbus protocol as the data transmission protocol. In order to decouple the development of the data acquisition system from the chip development, an FPGA based CPV-4 upper-tier chip emulator was designed based on the real chip's specifications. The emulator was used to verify the functionality of the data acquisition system, demonstrating the reliability and stability of the data acquisition system. The DAQ system will be used to validate the chip design and fabrication process of SOI-3D, and is also applicable for testing and validation of other complex pixel chips.
Key Words: CPV-4; Pixel sensor; Data Acquisition System; IPbus.
Speaker: Chang Xu -
181
Dolosse - A Modern, Scalable, and Extensible Data Acquisition and Management System for Nuclear Physics Experiments
Dolosse, a project funded by the National Research Foundation, is an innovative open-source Data Acquisition System (DAQ) specifically designed to meet the sophisticated requirements of contemporary nuclear physics research. This framework facilitates a high-throughput, fault-tolerant streaming service capable of handling the 'Big Data' attributes—volume, velocity, and variety—that characterize modern experimental physics data streams. By integrating with state-of-the-art Big Data technologies, Dolosse offers a comprehensive solution for real-time data analysis, visualization, and system monitoring. The system's architecture promises enhanced data integrity, reduced latency, and increased throughput, thereby enabling more complex and data-intensive experiments. Dolosse is projected as a pivotal tool for future research advancements in the global nuclear physics community.
Speaker: Thabang Mokoena -
182
The Beam commissioning of SC Cyclotron based Proton Therapy System with fast energy selection and Precise Gantry Positioning
Since 2016, a superconducting cyclotron based proton therapy system has been designed, construction, installation and commissioning at China Institute of Atomic Energy (CIAE). It includes a superconducting cyclotron CYCIAE-230, a beam line with a fast energy selection system, a 360 ° gantry, and a pencil beam scanning nozzle. And there is another beam line for proton irradiation, for example, used for space science research. In this paper, the overall design of the PT system will be introduced briefly. The results of the beam commissioning, from the cyclotron to the nozzle will be emphased. As early as Sept. 2020, the energy of proton beam accelerated by the superconducting cyclotron reached 231MeV; the 360° gantry had been tested by experts and found to have an isocenter of better than 0.3mm at any angle. After obtaining comprehensive commissioning permission in late November last year, we finished the test of the PT system with the following results: the energy of the cyclotron is 242 MeV, the energy range of the degrader is 71 MeV~242MeV, the maximum average beam intensity extracted is 462 nA, and the measured efficiency of the beam from the central region to outside the cyclotron is 74%; it is 45 ms the time interval varying one energy step of the degrader and 51 units of the magnets. The results will be presented in detail in the paper.
Speaker: Prof. Tianjue Zhang (China Institute of Atomic Energy) -
10:20
Coffee Break
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183
CANPS Award: ’50 years of Trigger/DAQ technologies (1970-2020) in HEP and medical fieldSpeaker: Mr Patrick Le Du (CEA - IRFU)
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184
Study of single-slope ADC using FPGA TDC for streaming readout data acquisition
The shift of data acquisition systems from traditional hardware-triggered ones to streaming readout ones will be mandatory for near-future experiments. We are developing a streaming data acquisition system and have already established it to measure hit arrival time and charge information using FPGA-based TDC and time-over-threshold (TOT). However, charge measurement with TOT has limited performance and is also subject to pulse pileup in high-rate environments. Improving the charge measurement performance is challenging because general waveform digitizer circuits are expensive. One of the low-cost solutions is a single-slope ADC (SS-ADC). SS-ADC is a waveform digitizer consisting of a comparator followed by a TDC. The aim of this paper is to investigate whether SS-ADC can achieve practical performance for nuclear and particle physics experiments. Various situations of signals, slopes, and methods to extract signal features were studied by using simulation and measurements with test boards. The SS-ADC performance found in this study will be presented.
Speaker: Tomonori Takahashi (Research Center for Nuclear Physics, Osaka University) -
185
Control of plasma vertical displacement based on neural network
For elongation plasma, the vertical displacement control is essential for the stable operation of tokamak devices. In this paper, a neural network model is used to rapidly detect vertical displacement recognition, and a new vertical displacement control algorithm is built by combining the method of neural network. To reduce latency and provide sufficient computing resources for the neural network, a high-speed acquisition and fast control system is designed. The new control system is confirmed in EAST experiments. The results show that in EAST different plasma discharge configurations, the vertical displacement can be accurately calculated and be controlled in effectively and quickly.
Speaker: Ms huihui song (institute of plasma physics)
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179
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12:50
Lunch
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15:00
Cocktail party & beach time at ICISE
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