Speaker
Description
In 1995, Zoller [1] suggested the realization of a quantum computer by means of using ions in a linear trap. Since linear traps are only capable of storing a few tens of ions, the transition to 2D surface traps will be essential for useful quantum computers. Hence, plentiful research was done already about micro-fabricated 2D surface traps in an industrial environment [2,3,4]. To pave the way to scalable quantum information processors using ion traps, control over a high number of qubits will be needed. Therefore, complexity and possible error sources are suspected to rise. We present two key concepts to improve on the quality of ion traps. Both have been implemented successfully at the industrial fabrication facilities of Infineon-Technologies in Villach.
In the process of automated optical inspection (AOI), a CCD camera images the entire wafer and creates a so called golden sample as an average of all ion traps. Every chip exhibiting deviations to the golden sample in range of a given resolution, is inked and discarded automatically.
In the final screening test, all ion traps are tested for electrical functionality. To that end, a dedicated probe-card places probe needles on all bond pads in order to perform a Kelvin-contact and applies predefined currents and voltages. Every electrode gets probed against each other with respect to its isolation- and connectivity specifications.
This scheme of quality control helps to introduce a higher standard in the fabrication of ion traps, making them more reliable and therefore facilitating experimental research.
[1] J. I. Cirac and P. Zoller. Quantum computations with cold trapped ions. Phys. Rev. Lett., 74:4091?
4094, May 1995.
[2] Philip C. Holz, Silke Auchter, Gerald Stocker, Marco Valentini, Kirill Lakhmanskiy, Clemens
Rössler, Paul Stampfer, Sokratis Sgouridis, Elmar Aschauer, Yves Colombe, and Rainer Blatt.
2d linear trap array for quantum information processing. Advanced Quantum Technologies,
3(11):2000031, sep 2020.
[3] J. Stuart, R. Panock, C.D. Bruzewicz, J.A. Sedlacek, R. McConnell, I.L. Chuang, J.M. Sage, and
J. Chiaverini. Chip-integrated voltage sources for control of trapped ions. Physical Review Applied,
11(2), feb 2019.
[4] K. K. Mehta, A. M. Eltony, C. D. Bruzewicz, I. L. Chuang, R. J. Ram, J. M. Sage, and J. Chiaverini.
Ion traps fabricated in a CMOS foundry. Applied Physics Letters, 105(4):044103, jul 2014.
