Conveners
ASIC
- Angelo Rivetti (Universita e INFN Torino (IT))
ASIC
- Walter Snoeys (CERN)
ASIC
- Ping Gui ()
ASIC
- Wladyslaw Dabrowski (AGH University of Science and Technology (PL))
The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that...
Following the RD53A demonstrator, the ItkPix (ATLAS) and CROC (CMS) pixel readout chips are being developed within the RD53 collaboration for the HL-LHC pixel detector upgrades of the two experiments. The two chips are based on a common design, called RD53B, in 65nm CMOS technology and are optimized for very high rate (3GHz/cm2) and radiation levels (>500Mrad). The ATLAS pre-production chip...
The RD53B pixel readout chip has been submitted for fabrication, meeting specifications of the ATLAS and the CMS experiments for HL-LHC upgrades. Performance characterization of a readout chip in terms of link data rate, average readout latency and efficiency of hit data is essential to evaluate operation of pixel sensors at an extreme interaction rate. At the same time it is complex due to...
For the CMS HGCAL, the final version of the 72-channel front-end ASIC (HGCROC3) was submitted in December 2020. HGCROC3 includes low-noise/high-gain preamplifier/shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge measurement over the linear range of the preamplifier. In the saturation range a discriminator and TDC provide the charge information from TOT (200ns dynamic range, 50ps...
Silicon detectors with excellent time resolution will play a critical role in future collider experiments, providing a new tool in event reconstruction. The Low Gain Avalanche Detectors (LGAD) have been demonstrated to provide the required time resolution and radiation tolerance. We will present the FCFD0 ASIC developed to read out LGAD signals. The FCFD0 utilizes Constant Fraction...
The Micro-Vertex Detector of the CBM experiment at FAIR/GSI requires very light detector stations equipped with highly granular and thin pixel sensors adapted to hostile running conditions. A specific CMOS pixel sensor, called MIMOSIS, is being developed for this purpose. Inspired by the ALPIDE sensor equipping the ALICE ITS, its design is adapted to higher hit rate and radiation tolerance....
This work presents the first measurements on the Time SPOT1ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32×32 channels hybrid-pixel matrix. Targeted to 4D-Tracking applications in High Energy Physics experiments, the system aims to achieve a timing resolution of 30 ps or better at a maximum event rate of 3 MHz/channel with a Data Driven...
We present the first results obtained with the FAST2 family of ASICs. The FAST2 ASIC family, designed in the 110 nm CMOS technology, has been optimized for the read-out of Ultra-Fast Silicon Detectors, aiming to achieve a combined total time resolution of less than 40 ps. In the FAST2 family, the ASIC (FAST2_A) presents 16 channels and has only the amplification stage with a timing jitter...
The front-end electronics of Ionization chamber for radiation protection demands challenging sensitivity requirements in the femtoampere range and a wide dynamic range. This work details the development trajectory that culminated in a single chip solution with current measurement capability spanning nine decades. The various Application Specific Integrated Circuits designed in the Radiation...
The readout electronics for the CMS Electromagnetic Calorimeter is
undergoing a re-design in order to cope with the LHC ugrade.
In particular, a fourfold increase in the sampling frequency
(from 40 to 160 MS/s) is required. Therefore a new readout ASIC
has been developed.
The ASIC, named LiTE-DTU, is designed in a CMOS 65 nm technology.
The LiTE-DTU embeds two 12 bits, 160 MS/s ADCs, a...
The Endcap Timing Readout Chip (ETROC) is being developed for the CMS MTD Endcap Timing Layer (ETL) for the HL-LHC, to process LGAD signals with time resolution down to 30ps per track. The ETROC1 is the first full chain precision timing prototype, including preamplifier and discriminator, as well as a new low power TDC design that performs time-of-arrival (TOA) and time-over-threshold (TOT)...
The use of precision timing measurements will be a major tool at the HL-LHC, where it will be used to suppress pile-up and to search for long-lived particles. To control a reference clock with sub-picosecond accuracy, we have fabricated in the TSMC 65nm process a digitally controlled phase shifter. It is composed of a chain of 66 cells, each with a digitally controlled planar wave guide with...
TOFHIR2 is the front-end ASIC for the barrel timing layer (BTL) of the MIP timing detector for the CMS upgrade for HL-LHC, aiming at 30-60 ps resolution throughout HL-LHC lifetime. The BTL consists of LYSO:Ce crystals coupled to SiPMs which will suffer radiation damage. Relative to the first version of the front-end ASIC (TOFHIR2A), TOFHIR2X implements improved circuitry for mitigation of the...
Gotthard-II is a charge-integrating microstrip detector developed for experiments and diagnostics at free-electron lasers using hard X-rays of 5 keV–20 keV. Its potential scientific applications include X-ray absorption/emission spectroscopy, energy dispersive experiments, as well as veto signal generation for pixel detectors. The Gotthard-II ASIC has been designed in several optimization...
