Although software and firmware co-simulation is gaining popularity, it is still not widely used in the FPGA designs.
This work presents easy and structured approach for software and firmware co-simulation for bus centric designs.
The proposed approach is very modular and software language agnostic.
The only requirement is that the firmware design is accessible via some kind of bus.
The concept...
During the High-Luminosity phase of the LHC, the CMS endcap calorimeter will be replaced by the High-Granularity Calorimeter (HGCAL). A first firmware for the back-end DAQ system of the CMS Phase-2 upgrade HGCAL was implemented in the Serenity ATCA hardware. The system is responsible not only for the readout of the detector but also for its slow control and timing. To facilitate system...
The CERN developed radiation-tolerant data transmission chip lpGBT will be used on the peripheral electronics board (PEB) of High Granularity Timing Detector (HGTD) in ATLAS. In order to configure the lpGBT on the PEB, we designed a dedicated isolated USB programmer. Compared with the 2 existing lpGBT configuration toolkits, piGBT and CERN USB-I2C dongle, the programmer has very good...
Within the Phase-II upgrade of the LHC, the readout electronics of the ATLAS LAr Calorimeters is prepared for high luminosity operation expecting a pile-up of up to 200 simultaneous pp interactions. Real-time processing of digitized pulses sampled at 40 MHz is thus performed using FPGAs.
To cope with the signal pile-up, new machine learning approaches are explored that outperform the optimal...
Proton-Sound-Detectors (ProSDs) sense (at <1 ms latency) the thermoacoustic signal generated by the fast energy deposition at the Bragg peak of proton beams penetrating energy absorbers.
ProSDs are especially promising for experimental monitoring of high pulse rate (FLASH) hadron therapy treatments working in-sync with the beam.
This paper presents a mixed-signal detector capable of sensing...
Modern DAQ systems typically use the FPGA-based PCIe cards to concentrate and deliver the data to a computer used as an entry node of the data processing network.
This paper presents a QEMU-based methodology for the co-development of the FPGA-based hardware part, the Linux kernel driver, and the data receiving application. That approach enables quick verification of the FPGA firmware...
The FrontEnd LInk eXchange (FELIX) is an FPGA-based data router designed to interface custom detector readout systems, and commodity switched networks as part of the ongoing upgrade of the ATLAS experiment at CERN. FELIX relies on synchronous data aggregation with GBT and lpGBT protocols to control and readout multiple detector front-ends. To facilitate validation and benchmarking, we designed...
A high density data acquisition system integrating over 2000 channels inside of a single OpenVPX crate is intended to be used in different applications e.g. gaseous or scintillator-based particle detectors. 14 payload slots, controller and data concentrator communicate one with other via multi-gigabit backplane. Each payload slot consists of a front module for digital and a rear transition...
