Speaker
Description
The MONOLITH ERC Advanced project aims at producing a monolithic silicon pixel ASIC with picosecond-level time stamping by using fast SiGe BiCMOS electronics and a novel sensor concept, the Picosecond Avalanche Detector (PicoAD). A first ASIC prototype, featuring fast electronics and hexagonal pixel with 100µm pitch, confirms that the PicoAD principle works and achieves time resolutions better than 20ps. Tests on the electronics and sensor optimization have driven to a new ASIC design with improved electronics and 50µm pixel pitch, aiming to a time resolution below 10ps. The architecture, simulations and measurements will be presented.
Summary (500 words)
The MONOLITH ERC advanced project aims at combining picosecond time stamping capabilities with the advantages of a fully monolithic, highly granular SiGe BiCMOS design. With respect to CMOS processes, the use of state-of-the-art Hetero-junction Bipolar Transistors to produce low-power, low-noise and ultra-fast amplifiers allows for an order of magnitude improvement of time stamping capabilities and enable new applications.
A novel sensor concept, the Picosecond Avalanche Detector (PicoAD), has been developed and patented to reach this goal. The main idea of the PicoAD is to place a very thin gain layer deep inside the sensor such that a uniform gain can be achieved over the entire pixel matrix, guaranteeing full fill-factor and high spatial resolution. Moreover, only a tiny fraction of the charge is amplified, reducing charge-collection noise and improving time resolution.
A proof-of-principle ASIC prototype with a PicoAD sensor with 15 µm active thickness has been produced in a 130nm silicon-germanium BiCMOS process from IHP microelectronics. The ASIC includes a matrix with variants of the electronics, including active and passive pixels, discrimination stage, programmable DACs for biasing and TDCs. The outputs of four passive pixels are accessible with off-chip drivers to investigate the analog pulses. These passive pixels have been used to characterize efficiency and timing performance of the device in laboratory and testbeam, demonstrating full pixel efficiency and a time resolution of approximately 20ps. Detailed measurement analysis indicated that the high gain and fast signals caused electronics cross-talk and instability at the off-chip driver stage.
An evolution of this first prototype ASIC has been produced. The off-chip driver design has been improved, and tests confirm that both electronic cross-talk and stability issues have been addressed correctly. The matrices have been tested with radioactive sources to characterize the gain and equivalent-noise charge of the variants of the front-end at different working points. The same ASIC will be produced on a substrate implementing an optimization of the PicoAD and will be available in Q1 2023.
The final target for the MONOLITH project includes the design and production of a large-scale ASIC with a time resolution below 10ps. In view of that, a third ASIC is currently being designed as a final prototyping stage. It will include matrices of hexagonal pixels with variations of the front-end. The pixel geometry will be modified by reducing the pixel pitch to 50µm and reducing the interpixel region by a factor of two to optimize the electric field in the sensor. The design will include a tunable double-threshold discriminator and novel picosecond-level TDC.
The results obtained with the proof-of-concept PicoAD and the design of the successive prototypes will be presented.
