Conveners
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
ASIC
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
ASIC
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Ping Gui
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
- Ping Gui
ASIC
- Ping Gui
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
- Ping Gui
HKROC is an ASIC designed to readout the photomultiplier tubes of the Hyper-Kamiokande experiment. With a large number of channels and stringent readout requirements in terms of noise, speed and dynamic range, the ASIC is very challenging and innovative. Each HKROC channel embeds low-noise preamplifier-shapers, a 10-bit SAR-ADC for the charge measurement (up to 2500 pC) and a TDC for the...
RD53 Collaboration is a joint effort between ATLAS and CMS that was
established in 2013, and extended in 2018, to develop readout chips
for the HL-LHC pixel detectors in 65nm technology.
Main operational constraints for the readout electronics are: the
extremely harsh radiation environment (1 Grad), high hit (3GHz/cm2)
and Trigger rates (4 MHz), high data rate readout (5 Gb/s).
This work...
The upgraded high-luminosity Large Hadron Collider (HL-LHC) requires a new radiation tolerant ATLAS Liquid Argon Calorimeter readout operating at 40MHz with 16-bit dynamic range. The COLUTA is a 65nm CMOS custom 8-channel 15-bit 40 MSPS ADC ASIC developed for this application, coupling a 3.5-bit Multiplying-DAC (MDAC) stage to a successive approximation register (SAR) ADC. A Digital Data...
ASICs are important components in many HEP detectors and their functional simulation ensures successful operation while minimizing the number of long production cycles. Three radiation-tolerant ASICs (HCC, AMAC, and ABC) will perform the front-end readout, monitoring, and control of the outer layers of the ITk Strip particle tracker for the HL-LHC ATLAS detector. Simulated verification with...
This contribution presents the results of the performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the final version of the Short-Strip readout ASIC for the CMS Outer-Tracker PS-module. The ASIC performance is characterised at different temperatures and operating conditions, at the die level as well as at the wafer level. The radiation evaluation comprises...
The ToASt ASIC is a 64 channel integrated circuit designed for the readout
of the Silicon Strips that will equip the Micro-Vertex Detector of the PANDA
experiment.
The ASIC is synchronous to a 160 MHz clock, which defines also the
time resolution. A common time stamp is distributed to all channels to
provide a common time reference for time of arrival and time over threshold...
ALTIROC2 is the first full-scale 225-channel ASIC prototype designed for LGAD (low Gain Avalanche Diodes) readout, as part of the new ATLAS HGTD detector foreseen for the High Luminosity-LHC upgrade. The scientific goals require to detect charges as small as 2 fC with a 95% efficiency and to exhibit a 25 ps jitter for 10 fC input charge with less than 5 mW/channel. The 2x2 cm² chip was...
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC1 has been extensively tested, another round of beam test is now on going at Fermilab since March 2022. The performance of ETROC1 will be summarized, with emphasis on the main issue learned on the 40MHz noise after bump bonded with LGAD sensor and most recent...
The CMS Detector will be upgraded for the HL-LHC to include a MIP Timing Detector (MTD), which will consist of barrel and endcap timing layers, BTL and ETL. The BTL sensors are based on LYSO:Ce scintillation crystals coupled to SiPMs read-out by TOFHIR2 ASICs in the front-end system. A resolution of 30 ps for MIP signals is expected at the beginning of HL-LHC operation, degrading to 60 ps at...
We present the timing measurements performed using the Timespot1 ASIC after hybridization onto a sensor pixel matrix featuring 32x32 channels. The ASIC is fabricated in CMOS 28-nm technology and integrates 1024 readout pixels, each equipped with a fast Analog Front End and a high-resolution TDC. The sensor is a matched matrix of 1024 3D silicon sensors, having pitch of 55 µm and processed in a...
The MOnolithic Stitched Sensor chip (MOSS) is a development prototype towards the innovative ITS3 vertexing detector for the ALICE experiment at the LHC. Designed using a 65 nm CMOS Imaging technology, it aims at profiting from the stitching technique to construct a single-die monolithic pixel detector of 1.4 cm x 26 cm. The MOSS chip is one of the prototypes developed within CERN-EP R&D to...
A series of monolithic active pixel sensor prototypes were manufactured in the TPSCo 65 nm ISC imaging process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade project. Each APTS chip contains a 4x4 pixel matrix with fast analog outputs buffered to individual pads. To explore the process and sensor characteristics, various pixel sizes (10um - 25um),...
The MONOLITH ERC Advanced project aims at producing a monolithic silicon pixel ASIC with picosecond-level time stamping by using fast SiGe BiCMOS electronics and a novel sensor concept, the Picosecond Avalanche Detector (PicoAD). A first ASIC prototype, featuring fast electronics and hexagonal pixel with 100µm pitch, confirms that the PicoAD principle works and achieves time resolutions better...
MiniCACTUS is a monolithic CMOS sensor designed for tagging Minimum Ionizing Particles at the 100 ps level. The sensor features an array of diodes, without internal amplification, of surface 1.0 mm² and 0.5 mm², with an analog front-end and discriminator per pixel. A time resolution of 88 ps has been measured on a 0.5 mm² pixel from a 200 µm-thick sensor tested at CERN. 300 micron and 200...
The design and measurement results of a SoC readout ASIC, called FLAME, developed for the electromagnetic calorimeter at the future linear collider are presented. The FLAME consists of 32 channels with variable gain front-end, fully differential shaper, and a 10-bit SAR ADC, working at 20 MSps, in each channel. All ADC samples are streamed out by two 5.2 Gbps serializers. Two testbeam...
The increase in the complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes are strong advocators for employing a System-on-Chip (SoC) design integration methodology. This contribution will present a survey of open-source RISC-V based SoC design platforms and the results of an evaluation study in terms of performance, power...
Transient fault tolerance verification is a crucial step in the design of radiation-tolerant ASICs for high-energy physics experiments. In this paper, we discuss a methodical approach toward the verification of transient fault tolerance of ASICs using industry-standard methodologies and tools. The framework for fault verification includes tools for fault enumeration, fault injection, and...
A bandgap voltage reference, an 8-bit binary-weighted Digital to Analog Converter (DAC), a rail-to-rail operation amplifier and a scalable low voltage signaling (SLVS) transmitter and receiverhave been developed as macro blocks in 28 nm CMOS technology for the future upgrades for the high luminosity LHC. This work summarizes the design approach at the schematic and layout level. Practical...
The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, All-digital Phase Locked Loop (PLL) and Clock and Data Recovery (CDR) architectures constitute a promising option for future High...
The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two "snapshots" of the delay line are taken by the register array with two strobes separated with a known time interval. With two measurements, propagation delays of each...
The TPSCo 65 nm ISC technology is under study in the framework of the CERN-EP on monolithic active pixel sensors (MAPS) for High Energy Physics (HEP) applications, and the ALICE ITS3 upgrade project, for which a wafer-scale stitched MAPS sensor is under development. This contribution presents designs and measurement results for Bandgap Reference (BGR) and Temperature Sensor (TS) prototypes...
We report the development of a Waveform Sampler (WS) including the design and measurement results. The WS is developed as part of the Endcap Timing Readout Chip (ETROC) for the CMS MTD Endcap Timing Layer (ETL) for the HL-LHC. One of the ETROC 16x16 pixels is equipped with the waveform sampler, to sample the pixel’s preamplifier output waveform at 2.56GS/s and convert it into digital domain....
