Conveners
Programmable Logic, Design Tools and Methods
- Salvatore Danzeca (CERN)
- Johan Alme (University of Bergen (NO))
Programmable Logic, Design Tools and Methods
- Salvatore Danzeca (CERN)
- Johan Alme (University of Bergen (NO))
The data link from the detectors to the back-end stage must keep up with the requirements from the upcoming generation of High Energy Physics experiments. Pushing the limit of the Non-Return-to-Zero (NRZ) modulated signals, a line rate of up to 28 Gbps can be realized. In this talk, the implementation of the DART28 demonstrator system based on FPGA platforms from Xilinx and Intel will be...
Neural Network (NN)-based inference deployed in FPGAs or ASICs is a powerful tool for real-time data processing and reduction. FPGAs or ASICs may be needed to meet difficult latency or power efficiency requirements in data acquisition or control systems. The software package, hls4ml, was designed to make deploying optimized NNs on FPGAs and ASICs accessible for domain applications. We will...
The FELIX system is used to interface the front-end electronics and the commodity hardware in the server farm. FELIX is using RDMA through RoCE to transmit data from its host servers to the Software Readout Driver using off-the-shelf networking equipment. In the current version of FELIX, RDMA communication is implemented using software on both ends of the links. Improvements of the data...
Timing and Fast Control (TFC) system for the Compressed Baryonic Matter (CBM) experiment is being developed with focus on low and deterministic data transmission latency. This helps to avoid congestion of the free-streaming Data Acquisition System (DAQ) system during occasional data bursts caused by the expected beam intensity fluctuations. Proven in latency-optimized experimental data...
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the functions of four Endcap Layer Readout Chips (ETROCs), each including a PLL, a fast command decoder, the pixel and global data readout, and an I2C target. Based on the actual ETROC design, the firmware is implemented and...
At the HL-LHC, the number of proton-proton collisions in one bunch-crossing (called pileup) increases significantly, putting more stringent requirements on the LHC detectors electronics and real-time data-processing capabilities. The ATLAS LAr calorimeter measures with an excellent resolution the energy of particles produced in LHC collisions. The energy is computed in real-time using optimal...
