The implementation of a 64-channel ASIC for the readout of Silicon Photomultipliers in space experiments is described. Each channel embeds 256 memory cells which sample the input information at 200 MS/s. A single cell includes a sampling capacitor, a single-slope analog-to-digital converter and a digital control logic. The digitization is carried out only if a trigger signal validates the time...
We present a high speed Phase Locked Loop (PLL) which is designed to provide high speed clock for a pixel chip to transmit the serial data off chip. The pixel chip is designed to read out the charge of a beam monitor which is part of the CSR external-target experiment at HIRFL in China. The PLL consists of a differential ring oscillator, a digital divider, three-state phase frequency detector,...
A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks of 40 MHz, 80 MHz, and 640 MHz in the ALTIROC chip. The phase shifter is a two-step architecture, consisting of a coarse-phase shifting and a fine-phase shifting with a 97.7 ps step. The fine delay is a DLL-based structure operating at 640 MHz. The clocks are programmable independently and share one DLL...
A line driver with configurable pre-emphasis is implemented in a 65nm CMOS process. The driver utilizes a three-tap Feed-Forward Equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the Unit Interval (UI) via an 8-stage Delay-Locked Loop (DLL) and digital interpolator (DI). One can also control the output amplitude and source impedance...
We present the design of a prototype MAPS sensor MIC6 based on a 55 nm Quad-well CMOS Image Sensor process for the high energy physics experiment vertex detector application. A new node-based, data-driven, parallel readout architecture is implemented to achieve high spatial resolution, fast readout, and low power consumption. The size of MIC6 is 2.8 mm × 2.8 mm, which contains a pixel matrix...
The Inner Tracker silicon strip detector (ITk Strips) is a part of the ATLAS upgrade for the HL-LHC. The detector readout and control is accomplished by the interaction of three on-module custom ASICs (ABCStarv1, HCCStarv1 and AMACstar). All ASICs are designed with protections against Single Event Errors. Their resilience at the system-level can be tested using the Board for Evaluation of...
The Concentrator Integrated Circuit (CIC) ASIC is a front-end chip for both Pixel-Strip (PS) and Strip-Strip (2S) modules of the future Phase-II CMS Outer Tracker upgrade at the High-Luminosity LHC (HL-LHC). This data aggregator, designed in 65nm CMOS technology, will be a key element of the tracker front-end chain. Two versions, CIC1 and CIC2, were tested successfully in 2019 and 2021...
The stability of the clock distributed by the first version of the Barrel Calorimeter Processor (BCP V1) to the front-end electronics has been evaluated and compared with the required performance as specified for the phase 2 upgrade of the CMS Barrel Electromagnetic Calorimeter (EB). The evaluation setup emulated a full clock branch of the planned EB system through multiple stages. The...
The new Muon-Central-Trigger-Processor-Interface (MUCTPI) is part of the upgrade of the ATLAS Level-1 trigger system for the upcoming run of the Large Hadron Collider at CERN. High-end FPGAs receive and process muon candidate information arriving on 208 high-speed optical serial links, while the board is controlled by a SoC. Processed trigger information and summary data are sent to other...
Serial Powering features the upcoming phase II HL-LHC upgrade in the ATLAS and CMS experiment. The conventional approach of placing the pixel modules in a parallel arrangement could not be established due to different limitations like restricted space requirements or radiation tolerance, which makes the design of a suitable DC/DC-converter challenging. To ensure that future DC/DC converters...
We present the architectural design, prototype fabrication and and first results for the High Pitch digitizer System-on-Chip (HPSoC). The HPSoC is a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip is being fabricated in 65nm technology and targets the following features:...
The CMS experiment will replace its endcap calorimeters with a High Granularity Endcap Calorimeter (HGCAL) as part of the upgrades for High Luminosity LHC. The HGCAL readout system includes the Endcap Trigger Concentrator (ECON-T) ASIC to help manage the immense data volume associated with the trigger path of this six-million channel “imaging” calorimeter. Each ECON-T ASIC handles 15.36 Gbps...
The University of Liverpool HV-CMOS R&D group develops depleted monolithic active pixel sensors (DMAPS) for use in high radiation environments. In this contribution, we will present an overview of results from the latest chip, UKRI-MPW0. The contribution will focus primarily on the design of three sub-circuits, a bipolar junction transistor (BJT) based bandgap reference (BGR), a fully CMOS...
The tight space constraints of the ATLAS ITk Pixel system motivate the design of large-scale flex circuits for carrying low-voltage power, high-voltage sensor bias, and command/data transmission. These circuits extend over long distances in the barrel or large areas in the endcap rings, and they pose unique design challenges. We report on the design and prototyping of large-scale flex circuits...
With the foreseen upgrades in HL-LHC, the Versatile Link Plus project was launched to streamline the upgrade of the current optical fibre links between the experiments and the counting room in order to reach higher data rates.
New fiber cabling plants have been designed in this framework for tight integration in experiment front ends and operation at higher radiation doses. These make use...
Motivated by upcoming large upgrade projects at PSI and due to increasing demands for performance (handling more data, faster processing) in various subsystems of the accelerator and beamlines, our electronics and control system experts had the task to evaluate alternatives to the existing VME technology and build a new portfolio of electronic hardware tools accordingly. CompactPCI-Serial was...
An FPGA-based DAQ has been developed for collecting position information from several position-sensitive RPCs to reconstruct the tracks of cosmic muons in a muon scattering tomography setup. An 8-channel ultra-fast preamplifier discriminator NINO ASIC has been used in the front-end for the acquisition of current signals induced on readout channels of the RPCs. The DAQ has been designed for...
The custom design, radiation and magnetic field tolerant step-down DC/DC converter system was developed to supply LV power for the ATLAS ITk Strip Detector segments. The system is modular and consists of custom frames with embedded cooling plates and insertable boards containing two or four output channels. Each channel comprises a 48-to-11 V DC/DC converter, hardware overcurrent and...
The CPPM group has long been designing and testing HV-CMOS blocks to complete monolithic chips in various technologies (TJ180, LF150, AMS) in the framework of several collaborations. In 2020, we participated in the MLR1 run in TowerJazz 65 nm technology through CERN’s EP-R&D WP1.2, by designing a ring oscillator test chip. Its aim is to characterize the standard cells of this technology and...
Heterogeneous SoC-FPGAs are extremely valuable in custom instrumentation. We present the joint development of the DTS-100G by DESY and KIT. It is built around a Xilinx Zynq Ultrascale Plus and offers all available high-speed transceivers using QSFP28, Firefly28G, FMC, and FMC+ interfaces. The board is not specialized to a single application and can be used as a generic DAQ platform for various...
With the High Luminosity upgrade of the LHC we expect increased instantaneous luminosities up to 5x10^34 cm^-2s^-1, or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of the three new muon sub-detectors. The readout electronics for ME0 must be designed to accommodate high data rates and...
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a 564 ps output rise time, and a projected jitter value on the order...
ATLAS detector Phase-II upgrade for the High Luminosity Large Hadron Collider (HL-LHC) affects all major ATLAS systems including the Trigger and Data Acquisition. As part of the Level-0 Trigger System, the Global Trigger uses the most advanced FPGAs and optical modules to provide high input and output bandwidth and substantial processing power. The Global Trigger Versatile Module (GVM) hosts...
Hamlet has developed a modular gamma detector that can be operated in a hostile environment. The system is based on a matrix of CsI crystals readout with thermalized SiPM, and a digitizer board designed for the Mu2e electromagnetic calorimeter and customized for this project. Front-end electronics is based on the MUSIC chip, a custom VLSI component developed by the University of Barcelona. The...
This study shows a pattern recognition system based on Hough transform implemented on last generations of FPGA families, as the Xilinx UltraScale+. This investigation started from the ATLAS HTT project, and now it is proposed in general for the LHC Phase-II trigger upgrades HEP experiments, especially to those which aim at fast tracking capabilities. We have designed a Hough transform software...
The hadron therapy is a powerful medical instrumentation for cancer treatment. For the effectiveness of the hadron treatment, it is important to control the energy released by particles for precisely tracking the Bragg peak point. The present contribution refers to the development of a custom detector for proton source characterization. The detector, placed at different distances from the...
The electronics of the ATLAS Tile Calorimeter will be replaced for the HL-LHC. The TileCal Phase-II upgrade project has undertaken an extensive R&D program. A Demonstrator module containing the upgraded on-detector readout electronics was built in 2014, evaluated during seven test beam campaigns, and inserted into the ATLAS experiment in 2019. The Demonstrator module was build with backward...
In order to meet power and heat budget in large multichannel detector systems, an early data reduction by the means of signal feature extraction is necessary.
We are contributing to this topic, studying different approaches from analog and digital signal processing, investigating the influence of parameters like bandwidth and digitizer resolution. In a second step, we are looking into the...
PLUME (Probe for LUminosity MEasurement) is a dedicated luminosity meter (luminometer) for the LHCb detector which will operate during Run 3 at a luminosity level five times higher than in the previous runs. It was designed to measure, in real time, the instantaneous luminosity with an accuracy better than 5 %.
The detector relies on the registration of Cherenkov light emitted...
LHCb is undergoing a major upgrade to cope with LHC RUN3's increased luminosities and a trigger-less 40 MHz read-out to improve on many world-best physics measurements. A light and homogeneous tracker based on plastic scintillating fibers (SciFi) driven by 524k SiPM channels is being installed downstream of the LHCb dipole magnet. A Test System is in use to ensure the Quality Control of each...
Developing and implementing algorithms for detector read-out using FPGAs is traditionally done by using a hardware description language like VHDL, Verilog, or System Verilog. In the proposed approach here, we discuss an alternative way using higher level languages like the Intel HLS Compiler. Intel HLS supports C++17 standard and is ideal to apply methods from Modern C++ to implement complex...
The ATLAS ZDC detectors located in the LHC tunnel detect far-forward neutrons from interactions during lead-lead collisions. PMT signals are transferred over fast air-core cable at distance of 200 m to electronics room. A new ZDC-LUCROD readout module is a 9U VME board capable of processing signals from 8 channels with an FADC sampling rate of 320 MHz. The primary modification wrt....
A new concept in charged particle detection is proposed to establish the availability of sensors with high spatial (20 μm) and time resolution (20 ps). The detector consists of a monolithic sensor tightly integrated with an analog front-end in BiCMOS technology. In this contribution, first results of simulations and tests of monolithic sensor made in IHP SG13G2 technology are presented. The...
Beyond Run$4$ of the LHC the instantaneous luminosity in the LHCb detector is going to be raised to $1.5\mathrm{x}10^{34}\mathrm{cm}^{-2}\mathrm{s}^{-1}$. To achieve stable operations and precise tracking, it is planned to upgrade the complete LHCb tracking system.
The downstream trackers have to be upgraded to withstand the increased radiation and occupancy at a similar or lower material...
Following the RD53A demonstrator, the ItkPix (ATLAS) and CROC (CMS) pixel readout chips are being developed within the RD53 collaboration for the HL-LHC pixel detector upgrades of the two experiments. The two chips are based on a common design, called RD53B, in 65nm CMOS technology and are optimized for very high rate (3GHz/cm2) and radiation levels (>500Mrad). The CMS pre-production chip...
We report on our latest developments of a planar fiber-chip-coupling scheme, using angle polished, polarization maintaining (PM) fibers. Most integrated photonic chip components are polarization sensitive and a suitable way to launch several wavelength channels to the chip with the same polarization is the use of PM fibers. Those impose several challenges at processing and handling to achieve...
The high-luminosity upgrade to the LHC (HL-LHC) requires an all new, silicon-based inner detector (ITk strips). The AMACStar is one of three radiation hard ASICs that will be installed on the ITk strip modules. Its function is to autonomously monitor and control the temperatures, voltages, and currents in the detector modules, an essential feature for the ITk detector modules. A comprehensive...
TSPC dynamic logic is widely used in high-speed circuits like high-speed SERDES or frequency dividers. TSPC flip-flops are characterized by their high operation speed and low power consumption when compared with static flip-flops. Due to the relatively high leakage currents in the modern CMOS process, the use of leakage protection techniques of the storage nodes of TSPC logic is mandatory. In...
The MALTA family of DMAPS produced in Tower 180 nm CMOS technology target radiation hard applications for the HL-LHC and beyond. Several process modifications and front-end improvements have resulted in radiation hardness up to 2e15 n/cm2 and time resolution below 2 ns, with uniform charge collection efficiency across the Pixel of size 36.4 x 36.4 um2 with a 3...
The CERN RD50 CMOS working group develops the RD50-MPW series of monolithic CMOS sensors for potential use in future high luminosity experiments such as HL-LHC and FCC-hh.
In this contribution, we will present an overview of the RD50 High Voltage-CMOS activities, focusing on the design of RD50-MPW3, the latest chip of this series, and the readout electronics beyond the chip. We will give a...
The CMS Phase II High-Granularity Calorimeter (HGCAL) relies on passive boards known as wagons to transmit signals from silicon sensor modules to upstream electronics for further processing. Such wagon boards face many design constraints that result in over 50 unique varieties, each of which requires the precise placement of dozens of components onto a PCB layout. A suite of tools has been...
A two-photon absorption (TPA) laser setup can nowadays be used to imitate radiation effects of high-energy particles by tightly focusing an ultrafast laser on a sensitive node of electronics. At a certain energy per pulse, a single-event effect (SEE) can occur. This paper proposes to measure the amount of electron-hole pairs generated in the component and the characteristics of the laser beam...
Precision timing at 10ps levels will be transformative at future collider experiments. In case of high-energy, high-luminosity hadron colliders, including Run5/6 upgrades of HL-LHC, an integrated four-dimensional tracker with timing resolution of 10-30ps can drastically reduce the combinatorial challenge of track reconstruction at very high pileup densities. 4D trackers and timing layers are...
For the High-Luminosity Large Hadron Collider, the trigger and data acquisition system of the CMS experiment will be entirely replaced. Novel design choices have been explored, including ATCA prototyping platforms with SoC controllers and newly available interconnect technologies with serial optical links with data rates up to 28 Gb/s. Trigger analyses will be performed through sophisticated...
*As part of the CMS Phase Two Outer Tracker upgrade, a test card was developed to test the sensor bias high voltage filters present in the PS-FEH-R hybrids. The test card can test up to four hybrids at the same time. The test functions are voltage measurement, leakage current measurement and resistance measurement. A software test procedure was written to control the card and to perform the...
This contributions presents the implementation of the CBM-TRD cluster finder. The cluster finder is implented with Vitis HLS in an FPGA.
The CBM experiment at FAIR will focus on rare probes of the QCD phase diagram at high net-baryon densities.
The free streaming DAQ has to process up-to 2 TB/s of raw data. This data undergo online event selection, where 4D track reconstruction is necessary....
COLDATA is the data concentrator ASIC for the Liquid Argon Time Projection Chamber (LArTPC) Far Detector of the Deep Underground Neutrino Experiment (DUNE). This ASIC will operate for its lifetime at cryogenic temperatures immersed in LAr. Two COLDATA, eight ColdADC, and eight LArASIC front-end ASICs are placed on each Front-End Motherboard (FEMB) in the LArTPC. Each COLDATA concentrates...
A high resolution W-Si preshower detector is proposed for the FASER experiment at CERN to enable the measurement of new physics signals related to Long Lived Particles. For this purpose, a 1.5x2.2 cm2 monolithic silicon active-pixel detector is being developed. The detector will integrate ultra-fast, low-noise front-end electronics in 65 μm side hexagonal pixels. The system is designed to read...
The CMS experiment 40MHz Scouting project is aimed at intercepting the data produced at the level of the detectors' front-end without the filters induced by hardware-based Triggers. A first 40MHz Scouting implementation is realized by reading a slice of the Drift Tube (DT) muon detector, equipped with so-called Phase-2 Upgrade front-end boards. The data are transferred via high-speed optical...
