Speaker
Description
Summary 500 words
The CMS Pixel detector system is to be upgraded in the first phase of LHC upgrades. An upgrade is needed to maintain readout efficiencies when the LHC begins to exceed a luminosity of approximately 1E34 cm^-2s^-1. Due to the changes to the front-end ReadOut Chip (ROC) that are necessary to improve the inefficiencies in the present readout scheme, it quickly became obvious that the upgraded system should operate using digital readout. The data-rate generated by the new system has been calculated to be 320 Mb/s per front-end module that houses 16 ROCs. Initially, it was thought that the Analogue Opto-Hybrid (AOH) used in the present Pixel system could simply be re-built as-is and used to transmit digital data at the increased rate. A key component of the AOH (its laser diode) is however no longer manufactured. It was thus decided to profit from the component selection studies being carried out in the framework of the Versatile Link project that have identified both functionally-suitable and sufficiently radiation-tolerant candidate components that would be suitable for use in the phase 1 Pixel optical link. Component selection is important as the single-mode optical fibres used in the present system must be re-used for the phase 1 upgrade.
With a candidate Transmitter Optical Sub-Assembly (TOSA) component identified by the Versatile Link project, the design of a new Pixel Opto-Hybrid (POH) has been carried out. The TOSA contains a Fabry-Pérot edge-emitting laser diode operating at 1310 nm that is rather similar to the one currently installed in CMS. Strict dimensional constraints on the POH come from the layout of the service tube in which the POH will be mounted. These constraints have led to the POH PCB design measuring 40 mm by 22.5 mm. The POH houses the same chipset as the present AOH, consisting of an Analogue Level Translator (ALT) and a Linear Laser Driver (LLD). Each POH needs two ALTs and two LLDs, each driving two TOSAs for a total of four readout link transmitters per POH.
A key validation step has been the measurement of the ability of the existing chipset (that was designed to transmit analogue data at 40 MHz) to operate correctly when transmitting digital data at 320 Mb/s and beyond. Testing of the POH has shown that although it is the ALT that has the lower bandwidth of the two ASICs, the output optical eye diagrams are wide open even at an elevated data-rate of 400 Mb/s.
The overall system performance has also been assessed by carrying out Bit Error Rate (BER) testing by transmitting different data patterns via the POH and a length of single-mode optical fibre to candidate optical receiver modules for use in the counting room. These tests have revealed the need for encoding of the transmitted data to improve their DC-balance and we have proposed the use of 4B/5B NRZI coding. Even with the attendant increase in data-rate to 400 Mb/s that this coding scheme brings, our tests have shown the POH-based link to operate with sufficient margin at the receiver to ensure link operation with a BER below 1E-12.
