Summary 500 words
AsAd system architecture includes 4 x 64Channels input ASIC (AGET) having individual adjustable polarity, gains, shaping, discriminator and pulser input. The pre-amp and filter can be either internal or external. Input signals are continuously sampled (100MHz) and read on 4 x 12 bit ADC (25MHz). The ADC also codes the multiplicity time sequence. A 64 channel register per AGET is read and allows a selective computed read-out window of the SCA. The front-end board is monitored by a FPGA. Its includes a built-in power supply with continuous monitoring, a calibration pulser and a set of synchronization and inspections lines.