Speaker
Description
Summary 500 words
In 2013 an additional layer, the Insertable B-Layer (IBL) will be added to the pixel detector of the ATLAS experiment at the LHC at CERN. For this fourth and innermost layer 448 newly developed pixel sensor chips (FE-I4) are used which will provide about 12 million pixel. For the readout of the IBL new off-detector electronics are needed as the FE-I4s feature an increased readout bandwidth which can not be handled by the current system. To provide a degree of backward compatibility the new system will keep the structure of VME card pairs: The back of crate card (BOC) establishes the optical interfaces to the detector front end as well as to the read out system (ROS) while the read out driver (ROD) manages data processing and calibration. Both cards, the BOC and the ROD, are currently under redesign and will feature modern FPGA technology, yielding an integration four times higher than the current system.
Based on the first prototype we present details of the design approach of the new BOC, focussed on the hardware used to provide all the needed functionalities. As replacement of the custom made optical plug-ins, used on the current BOC, commercial available 12-channel optical modules (SNAP12) are used and the SLINK protocol is embedded into the FPGAs of the new BOC, making the formerly used HOLA mezzanine cards obsolete. The task of synchronising the incoming data is shifted from custom delay ASICs to the FPGAs which will also perform the 8b10b decoding needed for the FE-I4 data stream (data from the previous FE-I3 chips is not encoded). As another new feature the new BOC will be equipped with an embedded local monitor board (ELMB) directly connected to the ATLAS detector control system (DCS) allowing to monitor e.g. temperatures on the BOC. Low pin count FPGA mezzanine connectors (LPC FMC) will be available to attach mezzanine cards for evaluation, debugging or possible upgrades.
