Digital Verification for FPGA and ASIC Designers
It is essential to verify the correct operation of a digital FPGA or ASIC design before it is manufactured. However, making sense of the verification methodologies, languages and tools used, can be challenging, when first encountered. The first part of this tutorial gives a brief overview of the current verification landscape, including verification objectives, simulation and formal verification approaches, the languages used and the tools required. It then introduces the main features of SystemVerilog – the most popular language used for verification today. The Universal Verification Methodology (UVM) is an IEEE standard which provides a library of base classes, a framework and rules that enable complex simulation environments to be created in SystemVerilog. Unfortunately, beginners often struggle to understand the multitude of features provided by UVM, so the tutorial will continue by introducing an “easier” subset of UVM and will show how this can be used to create a simple UVM testbench. A simulation-based approach is not the only way to verify a design: Formal verification is also possible in SystemVerilog! The tutorial will therefore give an overview of formal verification before concluding with recommendations on how to select the most appropriate verification approach for common design features.
- Current Verification Landscape
- The Verification Challenge
- Dynamic (Testbench simulation)
- Coverage
- Assertions
- Static (Formal Verification)
- Recommendations
- Class-Based SystemVerilog Verification
- Classes for transactions
- Classes for testbench components
- Connection to Device-Under-Test
- Inheritance
- Rand members and constraints
- Virtual methods
- Testbench architecture
- Universal Verification Methodology (UVM)
- Reusable verification components
- UVM simulation phases
- “Hello World” in UVM
- Creating a simple “agent”
- Configuration database and factory
- Writing a sequence for stimulus
- Putting it all together and running tests
- Formal Verification for Non-Specialists
- Learning to use Formal
- Writing properties
- Tackling State Space
- Under-constraining and Over-constraining
- Assume and Cover
- Considerations for use
- Conclusions and Recommendations
Dr David Long has been a key member of the Doulos technical team since 2001, specialising in Hardware Description Language-based design and verification. As well as developing, writing and presenting training courses in leading-edge methodologies for embedded SW development, FPGA, ASIC and SoC design and verification, David regularly contributes to technical papers, tutorials and conference presentations at major industry events world-wide. He has also provided project support and consultancy for industrial clients in the fields of digital/mixed-signal IC design and verification. Courses taught include: SystemVerilog, SystemC, UVM, VHDL, Verilog, VHDL-AMS, C and C++ Programming for Embedded Systems and Embedded System Security. David was co-author of the IEEE Standard 1666-2005 SystemC Language Reference Manual and wrote the draft LRM for the SystemC Control, Configuration and Inspection (CCI) working group. He has a PhD in Simulation of Mixed-Signal Circuits and a MSc in VLSI Design. Before joining Doulos, David worked for 10 years at a UK university where he was a Senior Lecturer in Microelectronics. In total, he has over 35 years experience of electronics design and verification in both industry and academia.
