Conveners
Trigger and Timing Distribution
- Alex Kluge (CERN)
Trigger and Timing Distribution
- Cristina Fernandez Bedoya (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))
A novel Data Acquisition (DAQ) system, known as Level-1 Data Scouting (L1DS), is being introduced as part of the Level-1 (L1) trigger of the CMS experiment. The L1DS system will receive the L1 intermediate primitives from the CMS Phase-2 L1 trigger on the DAQ-800 custom boards, designed for the Phase-2 central DAQ. Firmware is being developed for this purpose on the Xilinx VCU128 board, with...
Accurate clock and time distribution is a key requirement for self-triggered streaming data acquisition in the CBM experiment. This distribution is handled by the Timing and Fast Control (TFC) system by clock forwarding and broadcasting the common time over latency-deterministic optical links in a hierarchical FPGA network. The point-to-point optical connections are served by the...
The RHIC interaction rate at sPHENIX reaches around 3 MHz in pp collisions and requires the detector readout to reject events by a factor of over 200. Critical measurements often require the analysis of particles produced at low momentum. This prohibits adopting the traditional approach, where data rates are reduced through triggering on rare high momentum probes. We propose a new approach...
We present the deployment and testing of an autoencoder trained for unbiased detection of new physics signatures in the CMS Global Trigger test crate during LHC Run 3. The GT test crate is a copy of the main GT system, receiving the same input data, but whose output is not used to trigger the readout of CMS, providing a platform for thorough testing of new trigger algorithms on live data, but...
During the LHC Run-3 the LHCb software trigger is expected to reconstruct events at an average rate of 30 MHz. In view of future runs at even higher luminosities, LHCb established a testbed for new heterogeneous computing solutions for real-time event reconstruction within the current DAQ infrastructure. The most advanced of these sois a highly-parallelized custom tracking processor...
The baseline architecture for the ATLAS Phase-II upgrade has a single-level hardware trigger (Level-0 Trigger) with a maximum rate of 1 MHz and 10 μs latency. A full-function Global Common Module (GCM) prototype has been designed and implemented for the core part of the Level-0 Trigger, the Global Trigger. This GCM features two of the latest Adaptive Compute Acceleration Platform (ACAP)...
