HYLITE (High dYmamic range free electron Laser Imaging deTEctor) is a charge-integration pixel detector readout chip designed for SHINE (Shanghai high repetition rate XFEL and extreme light facility). The chip features a frame rate of 10kHz and a successive readout mode. HYLITE200S is the third prototype chip in the HYLITE series, including correlated double sampling circuits to improve noise...
The Cooling Storage Ring of the Heavy Ion Research Facility in Lanzhou (HIRFL-CSR) is constructed to study nuclear physics, atomic physics, interdisciplinary science, and relative applications. A Common Readout Unit (CRU) has been designed for HIRFL-CSR to reduce the development time, production cost, and maintenance difficulties of the data transmission at HIRFL. With the Xilinx the Virtex 7...
This contribution presents a pragmatic approach to read-out electronics for drift chambers used in particle physics experiments, specifically for the R3B experiment at GSI. The proposed circuit design uses discrete miniature SMD components and LVDS inputs of a low-cost FPGA to achieve a performance similar to the classic ASD8 ASIC. The presented approach offers an attractive solution for small...
High-resolution time-to-digital converters (TDCs) are required for time-of-flight measurements in many applications, including particle identification for high-energy physics. FPGA-based TDCs are popular for such applications but suffer from limited resolution and high power consumption compared to custom ASICs. Full-custom TDC designs can also be integrated within multi-channel or pixelated...
In this work, a low-power low-noise readout circuit for monolithic pixel detectors is presented. The design focuses on robustness and scalability for both reticle sized chips and stitched designs. The front-end includes a differential charge sensitive amplifier, a reset network and a two-stage discriminator. Threshold trimming is performed with a 3-bit DAC. The feedback capacitance is kept at...
Beam monitor is a sub detector for the CSR external-target experiment (CEE) at HIRFL, which is designed to monitor the beam status. A custom-designed pixel chip Topmetal-CEEv1 acts as the sensor for locating the position of each particle. In this paper, we present a prototype readout system for beam monitor. Injected pulse test and 241Am alpha test in the laboratory as well as beam test at...
The ASIC Design Group at RAL has commenced a three-year programme developing radiation-hardened 28nm circuits intended to provide verified building blocks for future projects. The aim of this programme is to complement and add to the CERN common IP library for 28nm. Our programme includes a range of utility circuits such as high precision amplifiers, a low power 12bit ADC for housekeeping,...
During the ATLAS phase II upgrade, the tracking system of the ATLAS experiment will be replaced by an all-silicon detector called the inner tracker (ITK) with a pixel detector as the most inner part. The monitoring data of the new system will be aggregated from an on-detector ASIC called Monitoring Of Pixel System (MOPS) and sent to the Detector Control System (DCS) using a new interface...
The HGTD aims to mitigate the effect of large pile-up interactions in the ATLAS Phase II upgrade project by providing accurate time measurements for tracks. However, since HGTD readout modules are unavailable during early stage, an FPGA-based front-end module emulator is designed as a substitute for system testing. This emulator also provides a flexible and cost-effective means to verify the...
The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype, TaichuPix, based on a column drain readout architecture, has been implemented to achieve high spatial resolution and fast readout. A 6-layer telescope made by TaichuPix-3 chips and baseline vertex...
Upgraded version of the CMS electromagnetic calorimeter (ECAL) Front-End (FE) card is designed to provide the lossless data streaming and reliable control and synchronization of the on-detector Very-Front-End (VFE) units.
The initial card design, validated in the beam tests in 2018-2019, was significantly modified to support the fast and reliable access to the VFE cards components for...
The Phase-2 Upgrade of the CMS Outer Tracker requires the production of 8000 Strip-Strip and 5880 Pixel-Strip modules, altogether incorporating 47520 hybrid circuits of 15 variants. Module design makes the potential repairs unfeasible; therefore, performing production-scale testing of the hybrids is essential. Accordingly, a scalable, crate-based test system was designed and manufactured,...
This contribution presents the latest advancements in integrating the Upstream Tracker in LHCb, including deploying control software, data acquisition firmware, decoding algorithm, and data analysis software. Additionally, the progress of different tasks is detailed, along with plans for the immediate future. The main focus of this talk is on the assessment of detector performance, including...
The Micro Vertex Detector is a key component of the PANDA experiment at FAIR. This contribution focuses on the development of the Module Data Concentrator (MDC) ASIC for the configuration, time distribution and readout of the silicon microstrip subdetector system of the PANDA Micro-Vertex Detector (MVD). A first version of the MDC architecture has been developed on FPGA and integrated with the...
NνDEx is a proposed experiment to hunt for the neutrinoless double beta decay of 82Se, with a high pressure SeF6 gaseous TPC. The readout and DAQ system are important parts of the experiment. The readout plane placed in one endcap of the TPC consists of around 15,000 sensors for charge measurement. It is crucial to read out data from all of these sensors efficiently. This paper will introduce...
The High-Luminosity LHC upgrade will have a new trigger system that utilizes detailed information from sub-detectors at the bunch crossing rate, which enables the Global Trigger (GT) to use high-precision trigger objects. Novel machine learning-based algorithms will also be included in the trigger system to achieve higher selection efficiency and detect unexpected signals. The focus of this...
In this work, we present the design, test system, and measurement results of the SMAUG_ND_1 ASIC. The described circuit implements an indirect energy measurement algorithm based on noise distribution measurement. The algorithm is similar to the threshold scan procedure but is done with a single pulse. The chip implements the matrix of 7x7 pixels each with 8 independent comparators and a size...
One of the main objectives of the Taishan Antineutrino Observatory (TAO) is to accurately measure the reactor neutrino energy spectrum to provide precise input to the Jiangmen Underground Neutrino Observatory (JUNO). In this study, we designed a full potential readout system for TAO based on the Klaus6 chip.We also developed a mockup prototype based on the design, which includes 4 chips (up to...
In this article we describe the measurement results on an “AARDVARC” prototype in 130 nm. AARDVARC is a multi-channel waveform digitizing and processing Application Specific Integrated Circuit (ASIC) front-end. We report on various performance metrics: fast sampling (10-14 Gsa/s), deep storage (32K samples), timing resolution (better than 5ps), low power consumption (<100mW/channel).
FABulous is an open-source eFPGA framework developed by the University of Manchester, enabling programmable digital logic to be integrated into ASIC designs. In 2023, our team plans to submit a 28nm CMOS ASIC and explore flatten versus hierarchical design using HVT devices for radiation hardening. This 28nm eFPGA design will use SUGOI and PGPv4 to program and move data in and out of the eFPGA....
In particle physics applications the photon beam interaction with various materials can produce electric charge which can be measured as current and be used to diagnose particle trajectories, beam intensity, beam profile, position, and stability. SIRIUS, the new 3 GeV fourth-generation Brazilian light source, will make use of hundreds of low-intensity measurement instruments. This work aims at...
The ALICE experiment at the CERN LHC will replace the three innermost layers of the Inner Tracker System (ITS) with an innovative vertexing detector. A single-die stitched monolithic pixel detector of 1.8 cm x 26 cm designed in 65 nm CMOS imaging technology will be used to build these layers. The data communication is done via the 1.8 cm edge of the detector. This contribution will focus on...
Ongoing developments in the field of radiation-tolerant high-speed transmitters (HST) aim to increase data rates above 25 Gb/s while increasing total ionizing dose (TID) tolerance above 1 Grad. The use of half-rate architecture imposes tight constraints on clock signal quality, in particular its duty cycle. Radiation degradation of transistors in the clock path causes duty cycle distortion...
The Beam Loss Monitoring system plays a crucial role in the CERN's Super Proton Synchrotron beam monitoring and machine protection. With the upcoming renovation of the system, the acquisition electronics can be based on an innovative ASIC designed by CERN. This paper presents the development of the control and digital processing electronics for this BLMASIC, reviews the architecture and design...
The drift chambers of the HADES spectrometer at GSI, Darmstadt/Germany, form its main tracking system. Designed more than twenty years ago, the whole front-end electronics chain is being replaced with state-of-the-art electronics.
The new analog signal processing is based on the PASTTREC ASIC, developed for the PANDA Straw Tube Tracker. The digitization of data happens in FPGA-based...
Arrays of superconducting sensors enable particle spectrum analysis with superior energy resolution. To efficiently acquire data from these sensors, the readout electronics operating at room temperature must perform multiple tasks, such as real-time frequency demodulation. We designed a Software-Defined Radio (SDR) system composed of an MPSoC board, an analog-to-digital conversion stage, and a...
The FastRICH is a readout chip designed by CERN and the University of Barcelona for the LS3 enhancements and the Upgrade II of the LHCb RICH detector. The 16-channel radiation-hard FastRICH will be capable of reading out MAPMTs, MCPs, and SiPMs, with peak hit rates up to 40MHz. The low-power readout, with 4 lpGBT/VTRx-compatible 1.28GHz SLVS output links, is optimized for bandwidth reduction,...
Crilin – a semi-homogeneous, longitudinally segmented highly granular electromagnetic calorimeter with Cherenkov PbF2 crystals has excellent timing and improved radiation resistance. A two-channel front-end prototype was tested at CERN-H2 with 120 GeV e- using PbF2 and PWO-UF crystals, yielding a single-cel timing resolution <30 ps for energy deposits <3 GeV. Crilin prototype consists of two...
The MicroTCA standard is widely used in the field of particle physics, and Advanced Mezzanine Card is the basic component of the MicroTCA system that requires module management control (MMC) for management. RISC-V is an open source ISA (Instruction Set Architecture) with extensive use. In this paper, we implement the MMC firmware on the MCU with RISC-V architecture. We build a universal...
Digital circuits exposed to radiation, e.g. at HL-LHC, are equipped with radiation-hardening features such as triple modular redundancy and error-correction codes. A method is developed to measure the single-event-upset cross section from error rate measurements in register banks that are protected by both ECC and TMR, taking into account the non-linear relationship between the cross section...
A new HV-CMOS pixel chip, called MightyPix, is being developed for the Mighty Tracker, an upgrade planned for LHCb in anticipation of the HL-LHC. Extensive research is ongoing to study the tracks and occupancy at the Mighty Tracker. This data is now used to simulate MightyPix’s performance in the LHCb environment, with focus on the digital readout. First results show an efficiency of 99.7% for...
The Mu2e CsI crystal calorimeter has high granularity, 10% energy and 500 ps timing resolution for 100 MeV electrons, and will achieve extremely high levels of reliability and stability and in a harsh operating environment. Each crystal is readout by two custom UV-extended SiPMs, with independent readout channels, coupled to custom front-end electronics boards, to provide individually...
In this contribution, we present the recent developments in the context of the OpenIPMC project, which proposes a free and open-source Intelligent Platform Management Controller (IPMC) software and an associated controller mezzanine for use in ATCA electronic boards. We discuss our experience in the operation of OpenIPMC on prototype boards designed for the upgrades of particle physics...
We will report the performance of Topmetal-S chip, a charge sensor specifically designed to directly sense ions for the high-pressure ion TPC of N$\nu$DEx experiment for neutrinoless double-beta decay search.The signal waveforms were investigated with various experiments and chip configurations.The equivalent noise charge of Topmetal-S is measured to be 120 e$^{-}$.Different ions species, both...
The interplay between High Energy Physics and Positron Emission Tomography detector development keeps providing encouraging outcomes of mutual interest, most notably observed in the development of scintillators, photon detectors, as well as the physics simulation tools. Our group develops PET detectors with the time of flight ability. In this work we present the 16-channel prototype which uses...
The consolidation of the Large Hadron Collider (LHC) beam position monitor (BPM) requires the deployment of about 5000 single-mode radiation-tolerant optical transmitters, working at 10 Gbps during 20 years of operation. While the use of the custom devices being designed at CERN remains the baseline for the project, 8 commercial of the shelf (COTS) optical transceivers have been evaluated as...
The MUX64 ASIC is a 64-to-1 analog multiplexer developed to expand the ADC input channels in the peripheral electronics of HGTD for the ATLAS Phase-II upgrade. The MUX64 chips will be used in the radiation field of high-luminosity pp collisions at LHC to an integrated luminosity of 4000 fb-1. The radiation hardness of MUX64 have been tested with 80 MeV protons and X-ray exposures...
Thirty-four RD53a Pixel detector modules arriving from different assembly sites are received at CERN in order to be integrated into the ITk demonstrator. The modules will go through different production validation stages, to monitor any performance degradation before the last stage with a full system test on the demonstrator. To mimic real detector services, multiple modules integrated on...
A charge-redistribution ADC with 10-bit resolution is implemented in the TPSCo 65nm CMOS process. The design is intended for flexible on-demand monitoring of vital system signals, such as temperature, in MAPS detectors. The successive approximation principle is implemented using only two matched capacitors and a trimming DAC, while an internal clock generator and digital sequencer are used to...
Advances in timing detector technology require new specialized readout electronics. Applications demand high rep rates, below 10 ps time of arrival resolution and, low power. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc. in collaboration with UC Santa Cruz has developed a prototype SiGe...
We report on our current developments towards a silicon photonic, 4-channel wavelength division multiplexed transmitter system with planar fiber chip coupling. The optical core components consisting of the photonic chip and the connecting V-groove mounted glass fibers were assembled with sub-micrometer accuracy on a glass plate with low thermal expansion for a stable fiber chip coupling. This...
After Run III the ATLAS detector will undergo a series of upgrades to cope with the harsher radiation environment and increased number of proton interactions in the High Luminosity-LHC. One of the key projects in this suite of upgrades is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out accurately and with extremely high rate. The Optosystem performs optical-...
This work presents the analog circuitry of the FastRICH ASIC, a 16-channel ASIC, developed in a 65 nm CMOS technology specifically designed for the RICH detector at LHCb to readout a wide range of detectors like Photomultiplier Tubes, to be used at the LHC Run 4 or SiPMs, candidates for Run 5. The front-end (FE) stage has an input impedance (Zin) below 50 Ω and an input dynamic range from 5 µA...
The ATLAS Strip Tracker for HL-LHC consists of individual modules that host silicon sensors and front-end electronics. The modules are then mounted on carbon-fiber substructures hosting up to 14 modules per side. An End-of-Substructure (EoS) card connects up to 28 data lines to the lpGBT and VL+ ASICs that provide data serialization and 10 GBit/s optical data transmission to the off-detector...
We present the development of the FBCM23 ASIC designed for the Phase-II upgrade of the Fast Beam Condition Monitoring (FBCM) system built at the CMS experiment. The FBCM system should provide reliable luminosity measurement with 1ns time resolution enabling the detection of beam-induced background. The FBCM23 ASIC comprises six channels of fast preamplifier working in transimpedance...
The ATLAS level-1 calorimeter trigger is a custom-built hardware system
that identifies events containing calorimeter-based physics objects,
including electrons, photons, taus, jets, and missing transverse energy.
In Run 3, L1Calo has been upgraded to process higher granularity
input data. The new trigger, currently running in parallel with the
legacy system, comprises several...
The assembly of the ATLAS Inner Tracker requires the construction of 19,000 silicon strip sensor detector modules in eight different geometries. Modules will be assembled and tested at 31 institutes on four continents, from sensors, readout chips and flexes. In order to adhere to the module specifications defined for sufficient tracking performance, a rigorous programme of quality control and...
Monitored Drift Tube (MDT) chambers for muons detection at ATLAS Experiment adopt analog front-end read-out electronics for precise-tracking/momentum measurements of detected particles [1]. State-of-the-art has historically used bipolar shaping electronics (at approximately 800 ns baseline recovery time [2]) that scarcely fits with High-Luminosity (HL) requirements where small-MDT (sMDT [3])...
The design of HVCMOS pixel detectors for measuring Galactic Cosmic Rays (GCR) and Solar Energetic Particles (SEP) in space is presented. The design goals are: (a) cover a very wide dynamic range (from ~0.5fC to pC) and (b) minimize the power consumption. Two pixel designs were implemented, one tailored to the measurement of high energy depositions due to impinging ions and one with high gain...
ECAL Barrel (EB) and MTD Barrel Timing Layer (BTL) subdetectors of the CMS are approaching series production of electronic boards, including voltage conditioning PCBs: LVR and PCC respectively. 2448 LVRs and 864 PCCs will be installed during LS3 of the LHC. These boards are hosting radiation-tolerant bPOL12V ASICs which convert a broad input voltage range into required voltage levels for...
